mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:49:52 +00:00
dabc6d838c
Add protected-clocks for GCC, change compatible string for SCC and modify clock names for better readability. Change-Id: I1d3c03ff192775932c5cba848260193bc0a73e47
1527 lines
34 KiB
Plaintext
1527 lines
34 KiB
Plaintext
#include <dt-bindings/clock/qcom,camcc-sc8180x.h>
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#include <dt-bindings/clock/qcom,dispcc-sm8250.h>
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#include <dt-bindings/clock/qcom,gcc-sc8180x.h>
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#include <dt-bindings/clock/qcom,gpucc-sm8150.h>
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#include <dt-bindings/clock/qcom,npucc-sm8150.h>
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#include <dt-bindings/clock/qcom,scc-sm8150.h>
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#include <dt-bindings/clock/qcom,videocc-sm8150.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/interconnect/qcom,icc.h>
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#include <dt-bindings/interconnect/qcom,sc8180x.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/soc/qcom,rpmh-rsc.h>
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/ {
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model = "Qualcomm Technologies, Inc. SDMSHRIKE";
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compatible = "qcom,sdmshrike";
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qcom,msm-name = "SDMSHRIKE";
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qcom,msm-id = <340 0x10000>;
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interrupt-parent = <&intc>;
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#address-cells = <2>;
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#size-cells = <2>;
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memory { device_type = "memory"; reg = <0 0 0 0>; };
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aliases {
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serial0 = &uart2;
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};
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cpus {
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#address-cells = <2>;
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#size-cells = <0>;
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CPU0: cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD0>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_0>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L2_0: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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L3_0: l3-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x400000>;
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cache-level = <3>;
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};
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};
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};
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CPU1: cpu@100 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x100>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD1>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_1>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L2_1: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU2: cpu@200 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x200>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD2>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_2>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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#cooling-cells = <2>;
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L2_2: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU3: cpu@300 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x300>;
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enable-method = "psci";
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cpu-idle-states = <&SILVER_OFF>;
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power-domains = <&CPU_PD3>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1024>;
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cache-size = <0x8000>;
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next-level-cache = <&L2_3>;
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qcom,freq-domain = <&cpufreq_hw 0 4>;
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L2_3: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x20000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU4: cpu@400 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x400>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD4>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x10000>;
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next-level-cache = <&L2_4>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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L2_4: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU5: cpu@500 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x500>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD5>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x10000>;
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next-level-cache = <&L2_5>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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L2_5: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU6: cpu@600 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x600>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD6>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x10000>;
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next-level-cache = <&L2_6>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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L2_6: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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CPU7: cpu@700 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x700>;
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enable-method = "psci";
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cpu-idle-states = <&GOLD_OFF>;
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power-domains = <&CPU_PD7>;
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power-domain-names = "psci";
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capacity-dmips-mhz = <1740>;
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cache-size = <0x10000>;
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next-level-cache = <&L2_7>;
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qcom,freq-domain = <&cpufreq_hw 1 4>;
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L2_7: l2-cache {
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compatible = "arm,arch-cache";
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cache-size = <0x80000>;
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cache-level = <2>;
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next-level-cache = <&L3_0>;
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};
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};
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cpu-map {
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cluster0 {
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core0 {
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cpu = <&CPU0>;
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};
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core1 {
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cpu = <&CPU1>;
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};
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core2 {
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cpu = <&CPU2>;
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};
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core3 {
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cpu = <&CPU3>;
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};
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};
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cluster1 {
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core0 {
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cpu = <&CPU4>;
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};
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core1 {
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cpu = <&CPU5>;
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};
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core2 {
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cpu = <&CPU6>;
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};
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core3 {
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cpu = <&CPU7>;
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};
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};
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};
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};
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idle-states {
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SILVER_OFF: silver-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <355>;
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exit-latency-us = <909>;
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min-residency-us = <3934>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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GOLD_OFF: gold-c4 { /* C4 */
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compatible = "arm,idle-state";
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idle-state-name = "rail-pc";
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entry-latency-us = <2411>;
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exit-latency-us = <1461>;
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min-residency-us = <4488>;
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arm,psci-suspend-param = <0x40000004>;
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local-timer-stop;
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};
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APSS_OFF: cluster-e3 { /* E3 */
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compatible = "domain-idle-state";
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idle-state-name = "llcc-off";
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entry-latency-us = <3263>;
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exit-latency-us = <6562>;
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min-residency-us = <9987>;
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arm,psci-suspend-param = <0x4100a344>;
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};
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};
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psci {
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compatible = "arm,psci-1.0";
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method = "smc";
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CPU_PD0: cpu-pd0 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD1: cpu-pd1 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD2: cpu-pd2 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD3: cpu-pd3 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD4: cpu-pd4 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD5: cpu-pd5 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD6: cpu-pd6 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CPU_PD7: cpu-pd7 {
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#power-domain-cells = <0>;
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power-domains = <&CLUSTER_PD>;
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};
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CLUSTER_PD: cluster-pd {
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#power-domain-cells = <0>;
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domain-idle-states = <&APSS_OFF>;
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};
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};
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chosen {};
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firmware: firmware { };
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reserved_memory: reserved-memory {
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#address-cells = <2>;
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#size-cells = <2>;
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ranges;
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hyp_mem: hyp_mem@85700000 {
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no-map;
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reg = <0x0 0x85700000 0x0 0x600000>;
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};
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xbl_aop_mem: xbl_aop_mem@85e00000 {
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no-map;
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reg = <0x0 0x85e00000 0x0 0x120000>;
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};
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flex_sec_apps_mem: flex_sec_apps_regions@85ffd000 {
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no-map;
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reg = <0x0 0x85ffd000 0x0 0x3000>;
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};
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aop_cmd_db: memory@85f20000 {
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compatible = "qcom,cmd-db";
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reg = <0x0 0x85f20000 0x0 0x20000>;
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no-map;
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};
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smem_region: smem@86000000 {
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no-map;
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reg = <0x0 0x86000000 0x0 0x200000>;
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};
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removed_regions: removed_regions@86200000 {
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no-map;
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reg = <0x0 0x86200000 0x0 0x5500000>;
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};
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pil_camera_mem: camera_region@8b700000 {
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no-map;
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reg = <0x0 0x8b700000 0x0 0x500000>;
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};
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pil_wlan_fw_mem: pil_wlan_fw_region@8bc00000 {
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no-map;
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reg = <0x0 0x8bc00000 0x0 0x180000>;
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};
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pil_npu_mem: pil_npu_region@8bd80000 {
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no-map;
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reg = <0x0 0x8bd80000 0x0 0x80000>;
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};
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pil_adsp_mem: pil_adsp_region@8be00000 {
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no-map;
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reg = <0x0 0x8be00000 0x0 0x1a00000>;
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};
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pil_modem_mem: modem_region@8d800000 {
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no-map;
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reg = <0x0 0x8d800000 0x0 0x9600000>;
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};
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pil_video_mem: pil_video_region@96e00000 {
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no-map;
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reg = <0x0 0x96e00000 0x0 0x500000>;
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};
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pil_slpi_mem: pil_slpi_region@97300000 {
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no-map;
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reg = <0x0 0x97300000 0x0 0x1400000>;
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};
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pil_ipa_fw_mem: pil_ipa_fw_region@98700000 {
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no-map;
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reg = <0x0 0x98700000 0x0 0x10000>;
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};
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pil_ipa_gsi_mem: pil_ipa_gsi_region@98710000 {
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no-map;
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reg = <0x0 0x98710000 0x0 0x5000>;
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};
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pil_gpu_mem: pil_gpu_region@98715000 {
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no-map;
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reg = <0x0 0x98715000 0x0 0x2000>;
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};
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pil_spss_mem: pil_spss_region@98800000 {
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no-map;
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reg = <0x0 0x98800000 0x0 0x100000>;
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};
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pil_cdsp_mem: cdsp_regions@98900000 {
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no-map;
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reg = <0x0 0x98900000 0x0 0x1400000>;
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};
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qseecom_mem: qseecom_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1400000>;
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};
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cont_splash_memory: splash_region {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "cont_splash_region";
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};
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disp_rdump_memory: disp_rdump_region@9c000000 {
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reg = <0x0 0x9c000000 0x0 0x02400000>;
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label = "disp_rdump_region";
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};
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adsp_mem: adsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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cdsp_mem: cdsp_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x400000>;
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};
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user_contig_mem: user_contig_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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qseecom_ta_mem: qseecom_ta_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x1000000>;
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};
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sp_mem: sp_region { /* SPSS-HLOS ION shared mem */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x800000>;
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};
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secure_display_memory: secure_display_region { /* Secure UI */
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0xA000000>;
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};
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dump_mem: mem_dump_region {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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size = <0 0x2400000>;
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};
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uefi_log: uefi_log@8bc00000 {
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reg = <0x0 0x8bc00000 0x0 0x10000>;
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label = "uefi_log";
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};
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/* global autoconfigured region for contiguous allocations */
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system_cma: linux,cma {
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compatible = "shared-dma-pool";
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alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
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reusable;
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alignment = <0x0 0x400000>;
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size = <0x0 0x2800000>;
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linux,cma-default;
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};
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};
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soc: soc { };
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};
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|
|
&soc {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges = <0 0 0 0xffffffff>;
|
|
compatible = "simple-bus";
|
|
|
|
intc: interrupt-controller@17a00000 {
|
|
compatible = "arm,gic-v3";
|
|
#interrupt-cells = <3>;
|
|
interrupt-controller;
|
|
#redistributor-regions = <1>;
|
|
redistributor-stride = <0x0 0x20000>;
|
|
reg = <0x17a00000 0x10000>, /* GICD */
|
|
<0x17a60000 0x100000>; /* GICR * 8 */
|
|
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
timer {
|
|
compatible = "arm,armv8-timer";
|
|
interrupts = <GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 2 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 3 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 0 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
clock-frequency = <19200000>;
|
|
};
|
|
|
|
timer@17c20000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
compatible = "arm,armv7-timer-mem";
|
|
reg = <0x17c20000 0x1000>;
|
|
clock-frequency = <19200000>;
|
|
|
|
frame@17c21000 {
|
|
frame-number = <0>;
|
|
interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c21000 0x1000>,
|
|
<0x17c22000 0x1000>;
|
|
};
|
|
|
|
frame@17c23000 {
|
|
frame-number = <1>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c23000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c25000 {
|
|
frame-number = <2>;
|
|
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c25000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c27000 {
|
|
frame-number = <3>;
|
|
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c26000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c29000 {
|
|
frame-number = <4>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c29000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2b000 {
|
|
frame-number = <5>;
|
|
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2b000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
frame@17c2d000 {
|
|
frame-number = <6>;
|
|
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
|
|
reg = <0x17c2d000 0x1000>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
clocks {
|
|
xo_board: xo-board {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <38400000>;
|
|
clock-output-names = "xo_board";
|
|
};
|
|
|
|
sleep_clk: sleep-clk {
|
|
compatible = "fixed-clock";
|
|
#clock-cells = <0>;
|
|
clock-frequency = <32000>;
|
|
clock-output-names = "sleep_clk";
|
|
};
|
|
};
|
|
|
|
qcom,msm-rtb {
|
|
compatible = "qcom,msm-rtb";
|
|
qcom,rtb-size = <0x100000>;
|
|
};
|
|
|
|
qcom,mpm2-sleep-counter@c221000 {
|
|
compatible = "qcom,mpm2-sleep-counter";
|
|
reg = <0xc221000 0x1000>;
|
|
clock-frequency = <32768>;
|
|
};
|
|
|
|
apps_rsc: rsc@18200000 {
|
|
label = "apps_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0x18200000 0x10000>,
|
|
<0x18210000 0x10000>,
|
|
<0x18220000 0x10000>;
|
|
reg-names = "drv-0", "drv-1", "drv-2";
|
|
qcom,drv-count = <3>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
power-domains = <&CLUSTER_PD>;
|
|
|
|
apps_rsc_drv2: drv@2 {
|
|
qcom,drv-id = <2>;
|
|
qcom,tcs-offset = <0xd00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <ACTIVE_TCS 2>,
|
|
<SLEEP_TCS 3>,
|
|
<WAKE_TCS 3>,
|
|
<CONTROL_TCS 1>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
rpmhcc: clock-controller {
|
|
compatible = "qcom,sm8150-rpmh-clk";
|
|
#clock-cells = <1>;
|
|
status = "okay";
|
|
};
|
|
|
|
apps_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
};
|
|
};
|
|
};
|
|
|
|
cluster-device {
|
|
compatible = "qcom,lpm-cluster-dev";
|
|
power-domains = <&CLUSTER_PD>;
|
|
};
|
|
|
|
disp_rsc: rsc@af20000 {
|
|
label = "disp_rsc";
|
|
compatible = "qcom,rpmh-rsc";
|
|
reg = <0xaf20000 0x10000>;
|
|
reg-names = "drv-0";
|
|
qcom,drv-count = <1>;
|
|
interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
disp_rsc_drv0: drv@0 {
|
|
qcom,drv-id = <0>;
|
|
qcom,tcs-offset = <0x1c00>;
|
|
channel@0 {
|
|
qcom,tcs-config = <SLEEP_TCS 1>,
|
|
<WAKE_TCS 1>,
|
|
<ACTIVE_TCS 2>,
|
|
<CONTROL_TCS 0>,
|
|
<FAST_PATH_TCS 0>;
|
|
};
|
|
|
|
disp_bcm_voter: bcm_voter {
|
|
compatible = "qcom,bcm-voter";
|
|
qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
|
|
};
|
|
};
|
|
};
|
|
|
|
pdc: interrupt-controller@b220000 {
|
|
compatible = "qcom,pdc";
|
|
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
|
|
qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>;
|
|
#interrupt-cells = <2>;
|
|
interrupt-parent = <&intc>;
|
|
interrupt-controller;
|
|
};
|
|
|
|
gcc: clock-controller@100000 {
|
|
compatible = "qcom,gcc-sc8180x", "syscon";
|
|
reg = <0x100000 0x1f0000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_cx_ao-supply = <&VDD_CX_LEVEL_AO>;
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>;
|
|
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk";
|
|
protected-clocks = <GCC_NPU_AXI_CLK_SRC>;
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
scc: clock-controller@2b10000 {
|
|
compatible = "qcom,sc8180x-scc";
|
|
reg = <0x2b10000 0x30000>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpucc: clock-controller@2c90000 {
|
|
compatible = "qcom,sc8180x-gpucc", "syscon";
|
|
reg = <0x2c90000 0x9000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
|
|
<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
|
|
clock-names = "bi_tcxo", "gcc_gpu_gpll0_clk_src", "gcc_gpu_gpll0_div_clk_src";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
npucc: clock-controller@9910000 {
|
|
compatible = "qcom,sm8150-npucc", "syscon";
|
|
reg = <0x9910000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_cx-supply = <&VDD_CX_LEVEL>;
|
|
vdd_gdsc-supply = <&npu_core_gdsc>;
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_NPU_GPLL0_DIV_CLK_SRC>,
|
|
<&gcc GCC_NPU_GPLL0_CLK_SRC>, <&gcc GCC_NPU_AXI_CLK>;
|
|
clock-names = "bi_tcxo", "gcc_npu_gpll0_div_clk_src",
|
|
"gcc_npu_gpll0_clk_src", "gcc_npu_axi_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
videocc: clock-controller@ab00000 {
|
|
compatible = "qcom,sm8150-videocc", "syscon";
|
|
reg = <0xab00000 0x10000>;
|
|
reg-names = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>;
|
|
clock-names = "cfg_ahb_clk", "bi_tcxo";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
camcc: clock-controller@ad00000 {
|
|
compatible = "qcom,sc8180x-camcc", "syscon";
|
|
reg = <0xad00000 0x20000>;
|
|
reg-name = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
vdd_mx-supply = <&VDD_MX_LEVEL>;
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
|
|
clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
dispcc: clock-controller@af00000 {
|
|
compatible = "qcom,sc8180x-dispcc", "syscon";
|
|
reg = <0xaf00000 0x20000>;
|
|
reg-names = "cc_base";
|
|
vdd_mm-supply = <&VDD_MMCX_LEVEL>;
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>, <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>;
|
|
clock-names = "cfg_ahb_clk", "bi_tcxo", "sleep_clk";
|
|
#clock-cells = <1>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
apsscc: syscon@182a0000 {
|
|
compatible = "syscon";
|
|
reg = <0x182a0000 0x1c>;
|
|
};
|
|
|
|
mccc: syscon@90b0000 {
|
|
compatible = "syscon";
|
|
reg = <0x90b0000 0x54>;
|
|
};
|
|
|
|
debugcc: debug-clock-controller@0 {
|
|
compatible = "qcom,sc8180x-debugcc";
|
|
qcom,gcc = <&gcc>;
|
|
qcom,videocc = <&videocc>;
|
|
qcom,camcc = <&camcc>;
|
|
qcom,dispcc = <&dispcc>;
|
|
qcom,npucc = <&npucc>;
|
|
qcom,gpucc = <&gpucc>;
|
|
qcom,apsscc = <&apsscc>;
|
|
qcom,mccc = <&mccc>;
|
|
clock-names = "xo_clk_src";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>;
|
|
#clock-cells = <1>;
|
|
};
|
|
|
|
cpufreq_hw: cpufreq@18323000 {
|
|
compatible = "qcom,cpufreq-hw";
|
|
reg = <0x18323000 0x1400>, <0x18325800 0x1400>;
|
|
reg-names = "freq-domain0", "freq-domain1";
|
|
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
|
|
clock-names = "xo", "alternate";
|
|
#freq-domain-cells = <2>;
|
|
};
|
|
|
|
config_noc: interconnect@1500000 {
|
|
reg = <0x1500000 0x7400>;
|
|
compatible = "qcom,sc8180x-config-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
system_noc: interconnect@1620000 {
|
|
reg = <0x1620000 0x21400>;
|
|
compatible = "qcom,sc8180x-system-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
ipa_virt: interconnect@0 {
|
|
compatible = "qcom,sc8180x-ipa-virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
camnoc_virt: interconnect@1 {
|
|
compatible = "qcom,sc8180x-camnoc-virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
aggre1_noc: interconnect@16e0000 {
|
|
reg = <0x16E0000 0x1A080>;
|
|
compatible = "qcom,sc8180x-aggre1-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_CARD_2_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>,
|
|
<&gcc GCC_AGGRE_USB3_MP_AXI_CLK>;
|
|
};
|
|
|
|
aggre2_noc: interconnect@1700000 {
|
|
reg = <0x1700000 0x3A080>;
|
|
compatible = "qcom,sc8180x-aggre2-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
compute_noc: interconnect@1716000 {
|
|
reg = <0x1716008 0x10>;
|
|
compatible = "qcom,sc8180x-compute-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
mmss_noc: interconnect@1740000 {
|
|
reg = <0x1740000 0x1C100>;
|
|
compatible = "qcom,sc8180x-mmss-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
dc_noc: interconnect@9160000 {
|
|
reg = <0x9160000 0x3200>;
|
|
compatible = "qcom,sc8180x-dc-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos";
|
|
qcom,bcm-voters = <&apps_bcm_voter>;
|
|
};
|
|
|
|
gem_noc: interconnect@9680000 {
|
|
reg = <0x9680000 0x58200>;
|
|
compatible = "qcom,sc8180x-gem-noc";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
|
|
};
|
|
|
|
mc_virt: interconnect@2 {
|
|
compatible = "qcom,sc8180x-mc-virt";
|
|
#interconnect-cells = <1>;
|
|
qcom,bcm-voter-names = "hlos", "disp";
|
|
qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
|
|
};
|
|
|
|
qupv3_id_1: geniqup@ac0000 {
|
|
compatible = "qcom,geni-se-qup";
|
|
reg = <0x00ac0000 0x6000>;
|
|
ranges;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
uart2: serial@a90000 {
|
|
compatible = "qcom,geni-debug-uart";
|
|
reg = <0x00a90000 0x4000>;
|
|
interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
soc-sleep-stats@c3f0000 {
|
|
compatible = "qcom,rpmh-sleep-stats-legacy";
|
|
reg = <0xc3f0000 0x400>;
|
|
ss-name = "modem", "adsp", "adsp_island",
|
|
"cdsp", "slpi", "slpi_island",
|
|
"apss";
|
|
};
|
|
|
|
tcsr_mutex_block: syscon@1f40000 {
|
|
compatible = "syscon";
|
|
reg = <0x1f40000 0x20000>;
|
|
};
|
|
|
|
tcsr_mutex: hwlock@1f40000 {
|
|
compatible = "qcom,tcsr-mutex";
|
|
syscon = <&tcsr_mutex_block 0 0x1000>;
|
|
#hwlock-cells = <1>;
|
|
};
|
|
|
|
smem: qcom,smem@8600000 {
|
|
compatible = "qcom,smem";
|
|
memory-region = <&smem_region>;
|
|
hwlocks = <&tcsr_mutex 3>;
|
|
};
|
|
|
|
apcs: syscon@17c0000c {
|
|
compatible = "syscon";
|
|
reg = <0x17c0000c 0x4>;
|
|
};
|
|
|
|
apss_shared: mailbox@17c00000 {
|
|
compatible = "qcom,sm8150-apss-shared";
|
|
reg = <0x17c00000 0x1000>;
|
|
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
qcom,secure-buffer {
|
|
compatible = "qcom,secure-buffer";
|
|
qcom,vmid-cp-camera-preview-ro;
|
|
};
|
|
|
|
qcom,mem-buf {
|
|
compatible = "qcom,mem-buf";
|
|
qcom,mem-buf-capabilities = "supplier";
|
|
qcom,vmid = <3>;
|
|
};
|
|
|
|
qcom,mem-buf-msgq {
|
|
compatible = "qcom,mem-buf-msgq";
|
|
};
|
|
|
|
aoss_qmp: power-controller@c300000 {
|
|
compatible = "qcom,sm8150-aoss-qmp";
|
|
reg = <0x0c300000 0x100000>;
|
|
interrupts = <GIC_SPI 389 IRQ_TYPE_EDGE_RISING>;
|
|
mboxes = <&apss_shared 0>;
|
|
#clock-cells = <0>;
|
|
#power-domain-cells = <1>;
|
|
};
|
|
|
|
qmp_aop: qcom,qmp-aop@c300000 {
|
|
compatible = "qcom,qmp-mbox";
|
|
qcom,qmp = <&aoss_qmp>;
|
|
label = "aop";
|
|
#mbox-cells = <1>;
|
|
};
|
|
|
|
sp_scsr_block: syscon@1880000 {
|
|
compatible = "syscon";
|
|
reg = <0x1880000 0x10000>;
|
|
};
|
|
|
|
intsp: qcom,qsee_irq {
|
|
compatible = "qcom,sm8150-qsee-irq";
|
|
|
|
syscon = <&sp_scsr_block>;
|
|
interrupts = <0 348 IRQ_TYPE_LEVEL_HIGH>,
|
|
<0 349 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
interrupt-names = "sp_ipc0",
|
|
"sp_ipc1";
|
|
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
};
|
|
|
|
qcom,qsee_irq_bridge {
|
|
compatible = "qcom,qsee-ipc-irq-bridge";
|
|
|
|
qcom,qsee-ipc-irq-spss {
|
|
qcom,dev-name = "qsee_ipc_irq_spss";
|
|
label = "spss";
|
|
interrupt-parent = <&intsp>;
|
|
interrupts = <1 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
qcom,glinkpkt {
|
|
compatible = "qcom,glinkpkt";
|
|
|
|
qcom,glinkpkt-apr-apps2 {
|
|
qcom,glinkpkt-edge = "adsp";
|
|
qcom,glinkpkt-ch-name = "apr_apps2";
|
|
qcom,glinkpkt-dev-name = "apr_apps2";
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-adsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <443>, <429>;
|
|
interrupts = <GIC_SPI 158 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ipc = <&apcs 0 10>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <2>;
|
|
|
|
adsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
adsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
qcom,smp2p-cdsp {
|
|
compatible = "qcom,smp2p";
|
|
qcom,smem = <94>, <432>;
|
|
interrupts = <GIC_SPI 576 IRQ_TYPE_EDGE_RISING>;
|
|
qcom,ipc = <&apcs 0 6>;
|
|
qcom,local-pid = <0>;
|
|
qcom,remote-pid = <5>;
|
|
|
|
cdsp_smp2p_out: master-kernel {
|
|
qcom,entry-name = "master-kernel";
|
|
#qcom,smem-state-cells = <1>;
|
|
};
|
|
|
|
cdsp_smp2p_in: slave-kernel {
|
|
qcom,entry-name = "slave-kernel";
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
};
|
|
};
|
|
|
|
wdog: qcom,wdt@17c10000 {
|
|
compatible = "qcom,msm-watchdog";
|
|
reg = <0x17c10000 0x1000>;
|
|
reg-names = "wdt-base";
|
|
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
cache-controller@9200000 {
|
|
compatible = "qcom,sdmshrike-llcc";
|
|
reg = <0x9200000 0x3d0000>, <0x9600000 0x50000>;
|
|
reg-names = "llcc_base", "llcc_broadcast_base";
|
|
cap-based-alloc-and-pwr-collapse;
|
|
};
|
|
|
|
qcom,chd {
|
|
compatible = "qcom,core-hang-detect";
|
|
label = "core";
|
|
qcom,threshold-arr = <0x18000058 0x18010058 0x18020058 0x18030058
|
|
0x18040058 0x18050058 0x18060058 0x18070058>;
|
|
qcom,config-arr = <0x18000060 0x18010060 0x18020060 0x18030060
|
|
0x18040060 0x18050060 0x18060060 0x18070060>;
|
|
};
|
|
|
|
cpu_pmu: cpu-pmu {
|
|
compatible = "arm,armv8-pmuv3";
|
|
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
qcom,pmu {
|
|
compatible = "qcom,pmu";
|
|
qcom,long-counter;
|
|
qcom,pmu-events-tbl =
|
|
< 0x0008 0xFF 0xFF 0xFF >,
|
|
< 0x0011 0xFF 0xFF 0xFF >,
|
|
< 0x0017 0xFF 0xFF 0xFF >,
|
|
< 0x002A 0xFF 0xFF 0xFF >,
|
|
< 0x1000 0xFF 0xFF 0xFF >;
|
|
};
|
|
|
|
ddr_freq_table: ddr-freq-table {
|
|
qcom,freq-tbl =
|
|
< 200000 >,
|
|
< 300000 >,
|
|
< 451000 >,
|
|
< 547000 >,
|
|
< 681000 >,
|
|
< 768000 >,
|
|
< 1017000 >,
|
|
< 1296000 >,
|
|
< 1555000 >,
|
|
< 1804000 >,
|
|
< 2092000 >;
|
|
};
|
|
|
|
llcc_freq_table: llcc-freq-table {
|
|
qcom,freq-tbl =
|
|
< 150000 >,
|
|
< 200000 >,
|
|
< 403000 >,
|
|
< 533000 >,
|
|
< 666000 >,
|
|
< 777000 >;
|
|
};
|
|
|
|
qcom_dcvs: qcom,dcvs {
|
|
compatible = "qcom,dcvs";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
ranges;
|
|
|
|
qcom_ddr_dcvs_hw: ddr {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <0>;
|
|
qcom,bus-width = <4>;
|
|
qcom,freq-tbl = <&ddr_freq_table>;
|
|
|
|
ddr_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&mc_virt MASTER_LLCC
|
|
&mc_virt SLAVE_EBI1>;
|
|
};
|
|
};
|
|
|
|
qcom_llcc_dcvs_hw: llcc {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <1>;
|
|
qcom,bus-width = <16>;
|
|
qcom,freq-tbl = <&llcc_freq_table>;
|
|
|
|
llcc_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
interconnects = <&gem_noc MASTER_APPSS_PROC
|
|
&gem_noc SLAVE_LLCC>;
|
|
};
|
|
};
|
|
|
|
qcom_l3_dcvs_hw: l3 {
|
|
compatible = "qcom,dcvs-hw";
|
|
qcom,dcvs-hw-type = <2>;
|
|
qcom,bus-width = <32>;
|
|
qcom,ftbl-row-size = <0x20>;
|
|
reg = <0x18321000 0x4000>, <0x18321110 0x500>;
|
|
reg-names = "l3-base", "l3tbl-base";
|
|
|
|
l3_dcvs_sp: sp {
|
|
compatible = "qcom,dcvs-path";
|
|
qcom,dcvs-path-type = <0>;
|
|
qcom,shared-offset = <0x0920>;
|
|
};
|
|
};
|
|
};
|
|
|
|
qcom_memlat: qcom,memlat {
|
|
compatible = "qcom,memlat";
|
|
|
|
ddr {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
qcom,sampling-path = <&ddr_dcvs_sp>;
|
|
qcom,miss-ev = <0x1000>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 200000 >,
|
|
< 576000 451000 >,
|
|
< 672000 768000 >,
|
|
< 864000 1017000 >,
|
|
< 1171200 1555800 >,
|
|
< 1267200 1804000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 200000 >,
|
|
< 576000 451000 >,
|
|
< 768000 768000 >,
|
|
< 960000 1017000 >,
|
|
< 1248000 1555000 >,
|
|
< 1593600 1804000 >,
|
|
< 1689600 1804000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold-compute {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 1593600 200000 >,
|
|
< 2016000 1017000 >,
|
|
< 2054400 2092000 >;
|
|
qcom,sampling-enabled;
|
|
qcom,compute-mon;
|
|
};
|
|
};
|
|
|
|
llcc {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
|
qcom,sampling-path = <&llcc_dcvs_sp>;
|
|
qcom,miss-ev = <0x2A>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 150000 >,
|
|
< 576000 200000 >,
|
|
< 672000 403000 >,
|
|
< 864000 533000 >,
|
|
< 1171200 666000 >,
|
|
< 1267200 777000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 200000 >,
|
|
< 576000 451000 >,
|
|
< 768000 768000 >,
|
|
< 960000 1017000 >,
|
|
< 1248000 1555000 >,
|
|
< 1593600 1804000 >,
|
|
< 1689600 2092000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
|
|
l3 {
|
|
compatible = "qcom,memlat-grp";
|
|
qcom,target-dev = <&qcom_l3_dcvs_hw>;
|
|
qcom,sampling-path = <&l3_dcvs_sp>;
|
|
qcom,miss-ev = <0x17>;
|
|
|
|
silver {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 300000 >,
|
|
< 576000 576000 >,
|
|
< 672000 768000 >,
|
|
< 864000 960000 >,
|
|
< 1171200 1228800 >,
|
|
< 1267200 1344000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
|
|
gold {
|
|
compatible = "qcom,memlat-mon";
|
|
qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
|
|
qcom,cpufreq-memfreq-tbl =
|
|
< 300000 300000 >,
|
|
< 576000 576000 >,
|
|
< 768000 768000 >,
|
|
< 960000 960000 >,
|
|
< 1248000 1228800 >,
|
|
< 1593600 1344000 >;
|
|
qcom,sampling-enabled;
|
|
};
|
|
};
|
|
};
|
|
|
|
bwmon_llcc: qcom,bwmon-llcc@90b6400 {
|
|
compatible = "qcom,bwmon4";
|
|
reg = <0x90b6400 0x300>, <0x90b6300 0x200>;
|
|
reg-names = "base", "global_base";
|
|
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,mport = <0>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <&qcom_llcc_dcvs_hw>;
|
|
};
|
|
|
|
bwmon_ddr: qcom,bwmon-ddr@90cd000 {
|
|
compatible = "qcom,bwmon5";
|
|
reg = <0x90cd000 0x1000>;
|
|
reg-names = "base";
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
qcom,hw-timer-hz = <19200000>;
|
|
qcom,count-unit = <0x10000>;
|
|
qcom,target-dev = <&qcom_ddr_dcvs_hw>;
|
|
};
|
|
};
|
|
|
|
&firmware {
|
|
qcom_scm {
|
|
compatible = "qcom,scm";
|
|
};
|
|
};
|
|
|
|
#include "sdmshrike-pinctrl.dtsi"
|
|
#include "sa8195-regulator.dtsi"
|
|
#include "sm8150-slpi-pinctrl.dtsi"
|
|
#include "sa8195-gdsc.dtsi"
|
|
#include "msm-arm-smmu-sdmshrike.dtsi"
|
|
|
|
&emac_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&pcie_0_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&pcie_1_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&pcie_2_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&pcie_3_gdsc {
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&ufs_card_2_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ufs_card_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&ufs_phy_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&usb30_mp_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&usb30_prim_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&usb30_sec_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_audio_tbu_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_tbu2_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_aggre_noc_mmu_pcie_tbu_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_sf_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu0_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&hlos1_vote_turing_mmu_tbu1_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&bps_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_0_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_1_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_2_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&ife_3_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&ipe_0_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&ipe_1_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&titan_top_gdsc {
|
|
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&mdss_core_gdsc {
|
|
clocks = <&gcc GCC_DISP_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_cx_gdsc {
|
|
status = "ok";
|
|
};
|
|
|
|
&gpu_gx_gdsc {
|
|
parent-supply = <&VDD_GFX_LEVEL>;
|
|
status = "ok";
|
|
};
|
|
|
|
&npu_core_gdsc {
|
|
clocks = <&gcc GCC_NPU_CFG_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
status = "ok";
|
|
};
|
|
|
|
&mvs0_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&mvs1_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
qcom,support-hw-trigger;
|
|
status = "ok";
|
|
};
|
|
|
|
&mvsc_gdsc {
|
|
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
|
|
clock-names = "ahb_clk";
|
|
parent-supply = <&VDD_MMCX_LEVEL>;
|
|
status = "ok";
|
|
};
|