Evolution-x-devices/kernel_oneplus_sm8550-devicetrees
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kernel_oneplus_sm8550-devic…/qcom/lemans.dtsi
Anjana Hari c4a54ee930 ARM: dts: msm: Enable primary UFS for Lemans 
Enable UFS0 instance for Lemans.

Change-Id: I1bf4f1f8246f1e538490e56af6caeaa9aa63c0f2
2022-10-12 11:31:05 +05:30

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#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,camcc-lemans.h>
#include <dt-bindings/clock/qcom,dispcc-lemans.h>
#include <dt-bindings/clock/qcom,gcc-lemans.h>
#include <dt-bindings/clock/qcom,gpucc-lemans.h>
#include <dt-bindings/clock/qcom,videocc-lemans.h>
#include <dt-bindings/interconnect/qcom,lemans.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/gpio/gpio.h>
/ {
model = "Qualcomm Technologies, Inc. Lemans";
compatible = "qcom,lemans";
qcom,msm-id = <532 0x10000>;
interrupt-parent = <&intc>;
#address-cells = <2>;
#size-cells = <2>;
memory { device_type = "memory"; reg = <0 0 0 0>; };
reserved_memory: reserved-memory { };
chosen: chosen { };
aliases {
serial0 = &qupv3_se10_2uart;
ufshc1 = &ufshc_mem; /* Embedded UFS slot */
};
soc: soc { };
firmware: firmware { };
cpus {
#address-cells = <2>;
#size-cells = <0>;
CPU0: cpu@0 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x0>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_0>;
L3_0: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
cache-size = <0x200000>;
};
};
};
CPU1: cpu@100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x100>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_1>;
L2_1: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_0>;
};
};
CPU2: cpu@200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x200>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_2>;
L2_2: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_0>;
};
};
CPU3: cpu@300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x300>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 0 4>;
next-level-cache = <&L2_3>;
L2_3: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_0>;
};
};
CPU4: cpu@10000 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10000>;
enable-method = "psci";
cache-size = <0x20000>;
cpu-release-addr = <0x0 0x90000000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_4>;
L2_4: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_1>;
L3_1: l3-cache {
compatible = "arm,arch-cache";
cache-level = <3>;
cache-size = <0x200000>;
};
};
};
CPU5: cpu@10100 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10100>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_5>;
L2_5: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_1>;
};
};
CPU6: cpu@10200 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10200>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_6>;
L2_6: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_1>;
};
};
CPU7: cpu@10300 {
device_type = "cpu";
compatible = "qcom,kryo";
reg = <0x0 0x10300>;
enable-method = "psci";
cpu-release-addr = <0x0 0x90000000>;
cache-size = <0x20000>;
qcom,freq-domain = <&cpufreq_hw 1 4>;
next-level-cache = <&L2_7>;
L2_7: l2-cache {
compatible = "arm,arch-cache";
cache-level = <2>;
cache-size = <0x80000>;
next-level-cache = <&L3_1>;
};
};
cpu-map {
cluster0 {
core0 {
cpu = <&CPU0>;
};
core1 {
cpu = <&CPU1>;
};
core2 {
cpu = <&CPU2>;
};
core3 {
cpu = <&CPU3>;
};
};
cluster1 {
core0 {
cpu = <&CPU4>;
};
core1 {
cpu = <&CPU5>;
};
core2 {
cpu = <&CPU6>;
};
core3 {
cpu = <&CPU7>;
};
};
};
};
};
&firmware {
scm {
compatible = "qcom,scm";
};
};
&reserved_memory {
#address-cells = <2>;
#size-cells = <2>;
ranges;
sail_ss_mem: sail_ss_region@80000000 {
no-map;
reg = <0x0 0x80000000 0x0 0x10000000>;
};
hyp_mem: hyp_region@90000000 {
no-map;
reg = <0x0 0x90000000 0x0 0x600000>;
};
xbl_boot_mem: xbl_boot_region@90600000 {
no-map;
reg = <0x0 0x90600000 0x0 0x200000>;
};
aop_image_mem: aop_image_region@90800000 {
no-map;
reg = <0x0 0x90800000 0x0 0x60000>;
};
aop_cmd_db_mem: aop_cmd_db_region@90860000 {
compatible = "qcom,cmd-db";
no-map;
reg = <0x0 0x90860000 0x0 0x20000>;
};
uefi_log: uefi_log_region@908b0000 {
no-map;
reg = <0x0 0x908b0000 0x0 0x10000>;
};
reserved_mem: reserved_region@908f0000 {
no-map;
reg = <0x0 0x908f0000 0x0 0xf000>;
};
secdata_apss_mem: secdata_apss_region@908ff000 {
no-map;
reg = <0x0 0x908ff000 0x0 0x1000>;
};
smem_mem: smem_region@90900000 {
no-map;
reg = <0x0 0x90900000 0x0 0x200000>;
};
cpucp_fw_mem: cpucp_fw_region@90b00000 {
no-map;
reg = <0x0 0x90b00000 0x0 0x100000>;
};
lpass_machine_learning_mem: lpass_machine_learning_region@93b00000 {
no-map;
reg = <0x0 0x93b00000 0x0 0xf00000>;
};
adsp_rpc_remote_heap_mem: adsp_rpc_remote_heap_region@94a00000 {
no-map;
reg = <0x0 0x94a00000 0x0 0x800000>;
};
pil_camera_mem: pil_camera_region@95200000 {
no-map;
reg = <0x0 0x95200000 0x0 0x500000>;
};
pil_adsp_mem: pil_adsp_region@95c00000 {
no-map;
reg = <0x0 0x95c00000 0x0 0x1e00000>;
};
pil_gdsp0_mem: pil_gdsp0_region@97b00000 {
no-map;
reg = <0x0 0x97b00000 0x0 0x1e00000>;
};
pil_gdsp1_mem: pil_gdsp1_region@99900000 {
no-map;
reg = <0x0 0x99900000 0x0 0x1e00000>;
};
pil_cdsp0_mem: pil_cdsp0_region@9b800000 {
no-map;
reg = <0x0 0x9b800000 0x0 0x1e00000>;
};
pil_gpu_mem: pil_gpu_region@9d600000 {
no-map;
reg = <0x0 0x9d600000 0x0 0x2000>;
};
pil_cdsp1_mem: pil_cdsp1_region@9d700000 {
no-map;
reg = <0x0 0x9d700000 0x0 0x1e00000>;
};
pil_cvp_mem: pil_cvp_region@9f500000 {
no-map;
reg = <0x0 0x9f500000 0x0 0x700000>;
};
pil_video_mem: pil_video_region@9fc00000 {
no-map;
reg = <0x0 0x9fc00000 0x0 0x700000>;
};
hyptz_reserved_mem: hyptz_reserved_region@beb00000 {
no-map;
reg = <0x0 0xbeb00000 0x0 0x11500000>;
};
tz_stat_mem: tz_stat_region@d0000000 {
no-map;
reg = <0x0 0xd0000000 0x0 0x100000>;
};
tags_mem: tags_region@d0100000 {
no-map;
reg = <0x0 0xd0100000 0x0 0x1200000>;
};
qtee_mem: qtee_region@d1300000 {
no-map;
reg = <0x0 0xd1300000 0x0 0x500000>;
};
trusted_apps_mem: trusted_apps_region@d1800000 {
no-map;
reg = <0x0 0xd1800000 0x0 0x3900000>;
};
dump_mem: mem_dump_region {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
reusable;
size = <0 0x3000000>;
};
/* global autoconfigured region for contiguous allocations */
linux,cma {
compatible = "shared-dma-pool";
alloc-ranges = <0x0 0x00000000 0x0 0xdfffffff>;
reusable;
alignment = <0x0 0x400000>;
size = <0x0 0x2000000>;
linux,cma-default;
};
};
&soc {
#address-cells = <1>;
#size-cells = <1>;
ranges = <0 0 0 0xffffffff>;
compatible = "simple-bus";
psci {
compatible = "arm,psci-1.0";
method = "smc";
};
intc: interrupt-controller@17a00000 {
compatible = "arm,gic-v3";
#interrupt-cells = <3>;
interrupt-controller;
#address-cells = <1>;
#size-cells = <1>;
ranges;
#redistributor-regions = <1>;
redistributor-stride = <0x0 0x20000>;
reg = <0x17a00000 0x10000>, /* GICD */
<0x17a60000 0x100000>; /* GICR * 8 */
interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
gic_its: gic-its@17a40000 {
compatible = "arm,gic-v3-its";
reg = <0x17a40000 0x20000>;
msi-controller;
#msi-cells = <1>;
};
};
pdc: interrupt-controller@b220000 {
compatible = "qcom,lemans-pdc", "qcom,pdc";
reg = <0xb220000 0x30000>, <0x17c000f0 0x64>;
qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>,
<55 306 4>, <59 312 3>, <62 374 2>,
<64 434 2>, <66 438 2>, <70 520 1>,
<73 523 1>, <118 568 6>, <124 609 3>,
<159 638 1>, <160 720 3>, <169 728 30>,
<199 416 2>, <201 449 1>, <202 89 1>,
<203 451 1>, <204 462 1>, <205 264 1>,
<206 579 1>, <207 653 1>, <208 656 1>,
<209 659 1>, <210 122 1>, <211 699 1>,
<212 705 1>, <213 450 1>, <214 643 2>,
<216 646 5>, <221 390 5>, <226 700 2>,
<228 440 1>, <229 663 1>, <230 524 2>,
<232 612 3>, <235 723 5>;
#interrupt-cells = <2>;
interrupt-parent = <&intc>;
interrupt-controller;
};
apps_rsc: rsc@18200000 {
label = "apps_rsc";
compatible = "qcom,rpmh-rsc";
reg = <0x18200000 0x10000>,
<0x18210000 0x10000>,
<0x18220000 0x10000>;
reg-names = "drv-0", "drv-1", "drv-2";
qcom,drv-count = <3>;
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
apps_rsc_drv2: drv@2 {
qcom,drv-id = <2>;
qcom,tcs-offset = <0xd00>;
channel@0 {
qcom,tcs-config = <ACTIVE_TCS 2>,
<SLEEP_TCS 3>,
<WAKE_TCS 3>,
<CONTROL_TCS 0>,
<FAST_PATH_TCS 0>;
};
rpmhcc: qcom,rpmhcc {
compatible = "qcom,lemans-rpmh-clk";
#clock-cells = <1>;
clock-names = "xo";
clocks = <&xo_board>;
status = "okay";
};
apps_bcm_voter: bcm_voter {
compatible = "qcom,bcm-voter";
};
};
};
arch_timer: timer {
compatible = "arm,armv8-timer";
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
<GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
clock-frequency = <19200000>;
};
memtimer: timer@17c20000 {
#address-cells = <1>;
#size-cells = <1>;
ranges;
compatible = "arm,armv7-timer-mem";
reg = <0x17c20000 0x1000>;
clock-frequency = <19200000>;
frame@17c21000 {
frame-number = <0>;
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
<GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c21000 0x1000>,
<0x17c22000 0x1000>;
};
frame@17c23000 {
frame-number = <1>;
interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c23000 0x1000>;
status = "disabled";
};
frame@17c25000 {
frame-number = <2>;
interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c25000 0x1000>;
status = "disabled";
};
frame@17c27000 {
frame-number = <3>;
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c27000 0x1000>;
status = "disabled";
};
frame@17c29000 {
frame-number = <4>;
interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c29000 0x1000>;
status = "disabled";
};
frame@17c2b000 {
frame-number = <5>;
interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2b000 0x1000>;
status = "disabled";
};
frame@17c2d000 {
frame-number = <6>;
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
reg = <0x17c2d000 0x1000>;
status = "disabled";
};
};
qcom,msm-imem@146d8000 {
compatible = "qcom,msm-imem";
reg = <0x146d8000 0x1000>;
ranges = <0x0 0x146d8000 0x1000>;
#address-cells = <1>;
#size-cells = <1>;
mem_dump_table@10 {
compatible = "qcom,msm-imem-mem_dump_table";
reg = <0x10 0x8>;
};
restart_reason@65c {
compatible = "qcom,msm-imem-restart_reason";
reg = <0x65c 0x4>;
};
dload_type@1c {
compatible = "qcom,msm-imem-dload-type";
reg = <0x1c 0x4>;
};
boot_stats@6b0 {
compatible = "qcom,msm-imem-boot_stats";
reg = <0x6b0 0x20>;
};
kaslr_offset@6d0 {
compatible = "qcom,msm-imem-kaslr_offset";
reg = <0x6d0 0xc>;
};
pil@94c {
compatible = "qcom,msm-imem-pil";
reg = <0x94c 0xc8>;
};
diag_dload@c8 {
compatible = "qcom,msm-imem-diag-dload";
reg = <0xc8 0xc8>;
};
};
tlmm: pinctrl@f000000 {
compatible = "qcom,lemans-pinctrl";
reg = <0xf000000 0x1000000>;
interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
gpio-controller;
#gpio-cells = <2>;
interrupt-controller;
#interrupt-cells = <2>;
};
wdog: qcom,wdt@17c10000 {
compatible = "qcom,msm-watchdog";
reg = <0x17c10000 0x1000>;
reg-names = "wdt-base";
interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
};
ipcc_mproc: qcom,ipcc@408000 {
compatible = "qcom,ipcc";
reg = <0x408000 0x1000>;
interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
interrupt-controller;
#interrupt-cells = <3>;
#mbox-cells = <2>;
};
clocks {
xo_board: xo_board {
compatible = "fixed-clock";
clock-frequency = <38400000>;
clock-output-names = "xo_board";
#clock-cells = <0>;
};
sleep_clk: sleep_clk {
compatible = "fixed-clock";
clock-frequency = <32000>;
clock-output-names = "sleep_clk";
#clock-cells = <0>;
};
pcie_0_pipe_clk: pcie_0_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_0_pipe_clk";
#clock-cells = <0>;
};
pcie_1_pipe_clk: pcie_1_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_1_pipe_clk";
#clock-cells = <0>;
};
pcie_phy_aux_clk: pcie_phy_aux_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "pcie_phy_aux_clk";
#clock-cells = <0>;
};
rxc0_ref_clk: rxc0_ref_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "rxc0_ref_clk";
#clock-cells = <0>;
};
rxc1_ref_clk: rxc1_ref_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "rxc0_ref_clk";
#clock-cells = <0>;
};
ufs_card_rx_symbol_0_clk: ufs_card_rx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_card_rx_symbol_0_clk";
#clock-cells = <0>;
};
ufs_card_rx_symbol_1_clk: ufs_card_rx_symbol_1_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_card_rx_symbol_1_clk";
#clock-cells = <0>;
};
ufs_card_tx_symbol_0_clk: ufs_card_tx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_card_tx_symbol_0_clk";
#clock-cells = <0>;
};
ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_rx_symbol_0_clk";
#clock-cells = <0>;
};
ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_rx_symbol_1_clk";
#clock-cells = <0>;
};
ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "ufs_phy_tx_symbol_0_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_prim_pipe_clk: usb3_phy_wrapper_gcc_usb30_prim_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_prim_pipe_clk";
#clock-cells = <0>;
};
usb3_phy_wrapper_gcc_usb30_sec_pipe_clk: usb3_phy_wrapper_gcc_usb30_sec_pipe_clk {
compatible = "fixed-clock";
clock-frequency = <1000>;
clock-output-names = "usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
#clock-cells = <0>;
};
};
gcc: clock-controller@100000 {
compatible = "qcom,lemans-gcc", "syscon";
reg = <0x100000 0xc7018>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
<&pcie_phy_aux_clk>, <&rxc0_ref_clk>, <&rxc1_ref_clk>, <&sleep_clk>,
<&ufs_card_rx_symbol_0_clk>, <&ufs_card_rx_symbol_1_clk>,
<&ufs_card_tx_symbol_0_clk>, <&ufs_phy_rx_symbol_0_clk>,
<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
<&usb3_phy_wrapper_gcc_usb30_prim_pipe_clk>,
<&usb3_phy_wrapper_gcc_usb30_sec_pipe_clk>;
clock-names = "bi_tcxo", "pcie_0_pipe_clk", "pcie_1_pipe_clk",
"pcie_phy_aux_clk", "rxc0_ref_clk", "rxc1_ref_clk", "sleep_clk",
"ufs_card_rx_symbol_0_clk", "ufs_card_rx_symbol_1_clk",
"ufs_card_tx_symbol_0_clk", "ufs_phy_rx_symbol_0_clk",
"ufs_phy_rx_symbol_1_clk", "ufs_phy_tx_symbol_0_clk",
"usb3_phy_wrapper_gcc_usb30_prim_pipe_clk",
"usb3_phy_wrapper_gcc_usb30_sec_pipe_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
camcc: clock-controller@ade0000 {
compatible = "qcom,lemans-camcc", "syscon";
reg = <0xade0000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
vdd_mxc-supply = <&VDD_MXC_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_CAMERA_AHB_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "iface", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc0: clock-controller@af00000 {
compatible = "qcom,lemans-dispcc0", "syscon";
reg = <0xaf00000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>, <&gcc GCC_DISP_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
dispcc1: clock-controller@22100000 {
compatible = "qcom,lemans-dispcc1", "syscon";
reg = <0x22100000 0x20000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&rpmhcc RPMH_CXO_CLK_A>,
<&sleep_clk>, <&gcc GCC_DISP1_AHB_CLK>;
clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
#clock-cells = <1>;
#reset-cells = <1>;
};
gpucc: clock-controller@3d90000 {
compatible = "qcom,lemans-gpucc", "syscon";
reg = <0x3d90000 0xa000>;
reg-name = "cc_base";
vdd_cx-supply = <&VDD_CX_LEVEL>;
vdd_mxa-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_CFG_AHB_CLK>,
<&gcc GCC_GPU_GPLL0_CLK_SRC>, <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
clock-names = "bi_tcxo", "iface", "gpll0_out_main", "gpll0_out_main_div";
#clock-cells = <1>;
#reset-cells = <1>;
};
videocc: clock-controller@abf0000 {
compatible = "qcom,lemans-videocc", "syscon";
reg = <0xabf0000 0x10000>;
reg-name = "cc_base";
vdd_mm-supply = <&VDD_MM_LEVEL>;
vdd_mx-supply = <&VDD_MXA_LEVEL>;
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_VIDEO_AHB_CLK>, <&sleep_clk>;
clock-names = "bi_tcxo", "iface", "sleep_clk";
#clock-cells = <1>;
#reset-cells = <1>;
};
cpufreq_hw: qcom,cpufreq-hw@18591000 {
compatible = "qcom,cpufreq-epss";
reg = <0x18591000 0x1000>, <0x18593000 0x1000>;
reg-names = "freq-domain0", "freq-domain1";
clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
clock-names = "xo", "alternate";
qcom,skip-enable-check;
qcom,lut-row-size = <4>;
#freq-domain-cells = <2>;
};
qcom,cpufreq-hw-debug@18591000 {
compatible = "qcom,cpufreq-hw-epss-debug";
qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
};
apsscc: syscon@182a0000 {
compatible = "syscon";
reg = <0x182a0000 0x1c>;
};
mccc: syscon@90ba000 {
compatible = "syscon";
reg = <0x90ba000 0x54>;
};
debugcc: debug-clock-controller@0 {
compatible = "qcom,lemans-debugcc";
qcom,gcc = <&gcc>;
qcom,camcc = <&camcc>;
qcom,dispcc0 = <&dispcc0>;
qcom,dispcc1 = <&dispcc1>;
qcom,gpucc = <&gpucc>;
qcom,videocc = <&videocc>;
qcom,apsscc = <&apsscc>;
qcom,mccc = <&mccc>;
clocks = <&rpmhcc RPMH_CXO_CLK>;
clock-names = "xo_clk_src";
#clock-cells = <1>;
};
clk_virt: interconnect@0 {
compatible = "qcom,lemans-clk_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mc_virt: interconnect@1 {
compatible = "qcom,lemans-mc_virt";
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
config_noc: interconnect@014C0000 {
compatible = "qcom,lemans-config_noc";
reg = <0x014C0000 0x13080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
system_noc: interconnect@01680000 {
compatible = "qcom,lemans-system_noc";
reg = <0x01680000 0x15080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
aggre1_noc:interconnect@016C0000 {
compatible = "qcom,lemans-aggre1_noc";
reg = <0x016C0000 0x18080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_NOC_QUPV3_AXI_CLK>,
<&gcc GCC_AGGRE_USB2_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
<&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>;
};
aggre2_noc: interconnect@01700000 {
compatible = "qcom,lemans-aggre2_noc";
reg = <0x01700000 0x1B080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_AGGRE_UFS_CARD_AXI_CLK>,
<&rpmhcc RPMH_IPA_CLK>;
};
pcie_anoc: interconnect@01760000 {
compatible = "qcom,lemans-pcie_anoc";
reg = <0x01760000 0xC080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gpdsp_anoc: interconnect@01780000 {
compatible = "qcom,lemans-gpdsp_anoc";
reg = <0x01780000 0xE080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
mmss_noc: interconnect@017A0000 {
compatible = "qcom,lemans-mmss_noc";
reg = <0x017A0000 0x40000>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
lpass_ag_noc: interconnect@03C40000 {
compatible = "qcom,lemans-lpass_ag_noc";
reg = <0x3C40000 0x17200>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
dc_noc: interconnect@090E0000 {
compatible = "qcom,lemans-dc_noc";
reg = <0x090E0000 0x5080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
gem_noc: interconnect@09100000 {
compatible = "qcom,lemans-gem_noc";
reg = <0x09100000 0xF6080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
clocks = <&gcc GCC_DDRSS_GPU_AXI_CLK>;
};
nspa_noc: interconnect@260C0000 {
compatible = "qcom,lemans-nspa_noc";
reg = <0x260C0000 0x16080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
nspb_noc: interconnect@2A0C0000 {
compatible = "qcom,lemans-nspb_noc";
reg = <0x2A0C0000 0x16080>;
#interconnect-cells = <1>;
qcom,bcm-voter-names = "hlos";
qcom,bcm-voters = <&apps_bcm_voter>;
};
vendor_hooks: qcom,cpu-vendor-hooks {
compatible = "qcom,cpu-vendor-hooks";
};
spmi_bus: qcom,spmi@c440000 {
compatible = "qcom,spmi-pmic-arb";
reg = <0xc440000 0x1100>,
<0xc600000 0x2000000>,
<0xe600000 0x100000>,
<0xe700000 0xa0000>,
<0xc40a000 0x26000>;
reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
interrupt-names = "periph_irq";
interrupt-controller;
#interrupt-cells = <4>;
#address-cells = <2>;
#size-cells = <0>;
cell-index = <0>;
qcom,channel = <0>;
qcom,ee = <0>;
};
thermal_zones: thermal-zones {
};
ufsphy_mem: ufsphy_mem@1d87000 {
reg = <0x1d87000 0xe10>;
reg-names = "phy_mem";
#phy-cells = <0>;
lanes-per-direction = <2>;
clock-names = "ref_clk_src",
"ref_clk",
"ref_aux_clk";
clocks = <&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_EDP_REF_CLKREF_EN>,
<&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
resets = <&ufshc_mem 0>;
status = "disabled";
};
ufshc_mem: ufshc@1d84000 {
compatible = "qcom,ufshc";
reg = <0x1d84000 0x3000>;
reg-names = "ufs_mem";
interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
phys = <&ufsphy_mem>;
phy-names = "ufsphy";
#reset-cells = <1>;
lanes-per-direction = <2>;
dev-ref-clk-freq = <0>; /* 19.2 MHz */
clock-names =
"core_clk",
"bus_aggr_clk",
"iface_clk",
"core_clk_unipro",
"core_clk_ice",
"ref_clk",
"tx_lane0_sync_clk",
"rx_lane0_sync_clk",
"rx_lane1_sync_clk";
clocks =
<&gcc GCC_UFS_PHY_AXI_CLK>,
<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
<&gcc GCC_UFS_PHY_AHB_CLK>,
<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
<&rpmhcc RPMH_CXO_CLK>,
<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
freq-table-hz =
<75000000 300000000>,
<0 0>,
<0 0>,
<75000000 300000000>,
<75000000 300000000>,
<0 0>,
<0 0>,
<0 0>,
<0 0>;
interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
interconnect-names = "ufs-ddr", "cpu-ufs";
qcom,ufs-bus-bw,name = "ufshc_mem";
qcom,ufs-bus-bw,num-cases = <26>;
qcom,ufs-bus-bw,num-paths = <2>;
qcom,ufs-bus-bw,vectors-KBps =
/*
* During HS G3 UFS runs at nominal voltage corner, vote
* higher bandwidth to push other buses in the data path
* to run at nominal to achieve max throughput.
* 4GBps pushes BIMC to run at nominal.
* 200MBps pushes CNOC to run at nominal.
* Vote for half of this bandwidth for HS G3 1-lane.
* For max bandwidth, vote high enough to push the buses
* to run in turbo voltage corner.
*/
<0 0>, <0 0>, /* No vote */
<922 0>, <1000 0>, /* PWM G1 */
<1844 0>, <1000 0>, /* PWM G2 */
<3688 0>, <1000 0>, /* PWM G3 */
<7376 0>, <1000 0>, /* PWM G4 */
<1844 0>, <1000 0>, /* PWM G1 L2 */
<3688 0>, <1000 0>, /* PWM G2 L2 */
<7376 0>, <1000 0>, /* PWM G3 L2 */
<14752 0>, <1000 0>, /* PWM G4 L2 */
<127796 0>, <1000 0>, /* HS G1 RA */
<255591 0>, <1000 0>, /* HS G2 RA */
<1492582 0>, <102400 0>, /* HS G3 RA */
<2915200 0>, <204800 0>, /* HS G4 RA */
<255591 0>, <1000 0>, /* HS G1 RA L2 */
<511181 0>, <1000 0>, /* HS G2 RA L2 */
<1492582 0>, <204800 0>, /* HS G3 RA L2 */
<2915200 0>, <409600 0>, /* HS G4 RA L2 */
<149422 0>, <1000 0>, /* HS G1 RB */
<298189 0>, <1000 0>, /* HS G2 RB */
<1492582 0>, <102400 0>, /* HS G3 RB */
<2915200 0>, <204800 0>, /* HS G4 RB */
<298189 0>, <1000 0>, /* HS G1 RB L2 */
<596378 0>, <1000 0>, /* HS G2 RB L2 */
/* As UFS working in HS G3 RB L2 mode, aggregated
* bandwidth (AB) should take care of providing
* optimum throughput requested. However, as tested,
* in order to scale up CNOC clock, instantaneous
* bindwidth (IB) needs to be given a proper value too.
*/
<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
<7643136 0>, <307200 0>; /* Max. bandwidth */
qcom,bus-vector-names = "MIN",
"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
"MAX";
reset-gpios = <&tlmm 149 GPIO_ACTIVE_LOW>;
resets = <&gcc GCC_UFS_PHY_BCR>;
reset-names = "rst";
iommus = <&apps_smmu 0x100 0x0>;
qcom,iommu-dma = "fastmap";
dma-coherent;
qcom,disable-lpm;
status = "disabled";
qos0 {
mask = <0xf0>;
vote = <44>;
};
qos1 {
mask = <0x0f>;
vote = <44>;
};
};
};
#include "lemans-4pmic-regulators.dtsi"
#include "lemans-gdsc.dtsi"
#include "lemans-pinctrl.dtsi"
#include "msm-arm-smmu-lemans.dtsi"
&cam_cc_titan_top_gdsc {
clocks = <&gcc GCC_CAMERA_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
status = "ok";
};
&disp0_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&disp0_cc_mdss_core_int2_gdsc {
clocks = <&gcc GCC_DISP_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&disp1_cc_mdss_core_gdsc {
clocks = <&gcc GCC_DISP1_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&disp1_cc_mdss_core_int2_gdsc {
clocks = <&gcc GCC_DISP1_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&gcc_emac0_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_emac1_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_0_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_pcie_1_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_ufs_card_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_ufs_phy_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb20_prim_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb30_prim_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gcc_usb30_sec_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
status = "ok";
};
&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc {
status = "ok";
};
&hlos1_vote_turing_mmu_tbu0_gdsc {
status = "ok";
};
&hlos1_vote_turing_mmu_tbu1_gdsc {
status = "ok";
};
&hlos1_vote_turing_mmu_tbu2_gdsc {
status = "ok";
};
&hlos1_vote_turing_mmu_tbu3_gdsc {
status = "ok";
};
&gpu_cc_cx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_CX_LEVEL>;
status = "ok";
};
&gpu_cc_gx_gdsc {
clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_GX_MXC_VOTER_LEVEL>;
status = "ok";
};
&video_cc_mvs0_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&video_cc_mvs0c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&video_cc_mvs1_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&video_cc_mvs1c_gdsc {
clocks = <&gcc GCC_VIDEO_AHB_CLK>;
clock-names = "ahb_clk";
parent-supply = <&VDD_MM_LEVEL>;
status = "ok";
};
&ufsphy_mem {
compatible = "qcom,ufs-phy-qmp-v4-waipio";
vdda-phy-supply = <&L4A>;
vdda-pll-supply = <&L1C>;
vdda-phy-max-microamp = <137000>;
vdda-pll-max-microamp = <18300>;
status = "ok";
};
&ufshc_mem {
vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
vdd-hba-fixed-regulator;
vcc-supply = <&L8A>;
vcc-voltage-level = <2504000 2506000>;
vcc-max-microamp = <1100000>;
vccq-supply = <&L4C>;
vccq-max-microamp = <1200000>;
vccq2-supply = <&S4A>;
vccq2-max-microamp = <800000>;
qcom,vddp-ref-clk-supply = <&L4C>;
qcom,vddp-ref-clk-max-microamp = <100>;
status = "ok";
};
#include "lemans-debug.dtsi"
#include "lemans-qupv3.dtsi"
&qupv3_se10_2uart {
status = "ok";
};
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