mirror of
https://github.com/Evolution-X-Devices/kernel_oneplus_sm8550-devicetrees
synced 2026-02-01 09:04:24 +00:00
95605511f5
As DMA addr pool for display unsecure context bank includes cont splah region it can be used by first commit. If we try to unmap the cont splash region after splash handoff while it is being used, SMMU faults are seen. This change leaves a hole at the cont splash in DMA address pool to avoid using this region for unsec_fbs. Change-Id: Ifc7e1875d5def8bde0b94589b37e78007a0312b6
251 lines
6.8 KiB
Plaintext
251 lines
6.8 KiB
Plaintext
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
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#include <dt-bindings/clock/qcom,dispcc-crow.h>
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#include <dt-bindings/clock/qcom,gcc-crow.h>
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#include <dt-bindings/interconnect/qcom,crow.h>
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#include <dt-bindings/clock/qcom,rpmh.h>
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#include <dt-bindings/clock/qcom,tcsrcc-kalama.h>
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#include "crow-sde-common.dtsi"
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&soc {
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ext_disp: qcom,msm-ext-disp {
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compatible = "qcom,msm-ext-disp";
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ext_disp_audio_codec: qcom,msm-ext-disp-audio-codec-rx {
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compatible = "qcom,msm-ext-disp-audio-codec-rx";
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};
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};
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qcom_msmhdcp: qcom,msm_hdcp {
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compatible = "qcom,msm-hdcp";
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};
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sde_dp: qcom,dp_display@ae90000 {
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cell-index = <0>;
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compatible = "qcom,dp-display";
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usb-phy = <&usb_qmp_dp_phy>;
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qcom,ext-disp = <&ext_disp>;
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qcom,altmode-dev = <&altmode 0>;
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usb-controller = <&usb0>;
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reg = <0xae90000 0x0fc>,
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<0xae90200 0x0c0>,
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<0xae90400 0x770>,
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<0xae91000 0x098>,
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<0x88eaa00 0x200>,
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<0x88ea200 0x200>,
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<0x88ea600 0x200>,
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<0x88ea000 0x200>,
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<0x88e8000 0x20>,
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<0x0aee1000 0x034>,
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<0xae91400 0x098>,
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<0xaf09000 0x14>;
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reg-names = "dp_ahb", "dp_aux", "dp_link",
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"dp_p0", "dp_phy", "dp_ln_tx0", "dp_ln_tx1",
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"dp_pll", "usb3_dp_com", "hdcp_physical",
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"dp_p1", "gdsc";
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interrupt-parent = <&mdss_mdp>;
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interrupts = <12 0>;
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#clock-cells = <1>;
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clocks = <&dispcc DISP_CC_MDSS_DPTX0_AUX_CLK>,
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<&rpmhcc RPMH_CXO_CLK>,
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<&tcsrcc TCSR_USB3_CLKREF_EN>,
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<&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX0_LINK_INTF_CLK>,
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<&sde_dp 0>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC>,
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<&sde_dp 1>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL0_CLK>,
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<&dispcc DISP_CC_MDSS_DPTX0_PIXEL1_CLK>;
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clock-names = "core_aux_clk", "rpmh_cxo_clk", "core_usb_ref_clk_src",
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"core_usb_pipe_clk", "link_clk", "link_clk_src", "link_iface_clk",
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"link_parent", "pixel_clk_rcg", "pixel_parent", "pixel1_clk_rcg",
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"strm0_pixel_clk", "strm1_pixel_clk";
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qcom,pll-revision = "4nm-v1";
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qcom,phy-version = <0x600>;
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qcom,aux-cfg0-settings = [20 00];
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qcom,aux-cfg1-settings = [24 13];
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qcom,aux-cfg2-settings = [28 A4];
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qcom,aux-cfg3-settings = [2c 00];
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qcom,aux-cfg4-settings = [30 0a];
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qcom,aux-cfg5-settings = [34 26];
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qcom,aux-cfg6-settings = [38 0a];
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qcom,aux-cfg7-settings = [3c 03];
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qcom,aux-cfg8-settings = [40 b7];
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qcom,aux-cfg9-settings = [44 03];
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qcom,max-pclk-frequency-khz = <675000>;
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qcom,widebus-enable;
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qcom,dsc-feature-enable;
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qcom,fec-feature-enable;
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qcom,dsc-continuous-pps;
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qcom,qos-cpu-mask = <0xf>;
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qcom,qos-cpu-latency-us = <300>;
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vdda-1p2-supply = <&L4B>;
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vdda-0p9-supply = <&L3B>;
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vdda_usb-0p9-supply = <&L2B>;
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vdd_mx-supply = <&VDD_MXA_LEVEL>;
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dp_phy_gdsc-supply = <&gcc_usb3_phy_gdsc>;
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qcom,ctrl-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,ctrl-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-1p2";
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qcom,supply-min-voltage = <1200000>;
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qcom,supply-max-voltage = <1200000>;
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qcom,supply-enable-load = <30100>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,phy-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,phy-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdda-0p9";
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qcom,supply-min-voltage = <912000>;
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qcom,supply-max-voltage = <912000>;
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qcom,supply-enable-load = <115000>;
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qcom,supply-disable-load = <0>;
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};
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qcom,phy-supply-entry@1 {
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reg = <1>;
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qcom,supply-name = "vdda_usb-0p9";
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qcom,supply-min-voltage = <880000>;
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qcom,supply-max-voltage = <880000>;
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qcom,supply-enable-load = <323000>;
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qcom,supply-disable-load = <0>;
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};
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};
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qcom,pll-supply-entries {
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#address-cells = <1>;
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#size-cells = <0>;
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qcom,pll-supply-entry@0 {
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reg = <0>;
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qcom,supply-name = "vdd_mx";
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qcom,supply-min-voltage =
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<RPMH_REGULATOR_LEVEL_TURBO>;
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qcom,supply-max-voltage =
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<RPMH_REGULATOR_LEVEL_MAX>;
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qcom,supply-enable-load = <0>;
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qcom,supply-disable-load = <0>;
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};
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};
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};
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sde_rscc: qcom,sde_rscc@af20000 {
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cell-index = <0>;
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compatible = "qcom,sde-rsc";
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reg = <0xaf20000 0x4d6c>,
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<0xaf30000 0x3fd4>;
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reg-names = "drv", "wrapper";
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qcom,sde-rsc-version = <5>;
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qcom,sde-dram-channels = <2>;
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vdd-supply = <&disp_cc_mdss_core_gdsc>;
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clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
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clock-names = "vsync_clk", "gdsc_clk", "iface_clk";
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qcom,msm-bus,active-only;
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interconnects =
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<&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>;
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interconnect-names = "qcom,sde-data-bus0";
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};
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smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
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compatible = "qcom,smmu_sde_unsec";
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iommus = <&apps_smmu 0x1c00 0x2>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xb7fe0000 0xbab00000 0x45500000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-earlymap; /* for cont-splash */
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dma-coherent;
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};
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smmu_sde_sec: qcom,smmu_sde_sec_cb {
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compatible = "qcom,smmu_sde_sec";
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iommus = <&apps_smmu 0x1c01 0x0>;
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qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
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qcom,iommu-faults = "non-fatal";
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qcom,iommu-vmid = <0xa>;
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};
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};
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&mdss_mdp {
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clocks =
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<&gcc GCC_DISP_HF_AXI_CLK>,
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<&dispcc DISP_CC_MDSS_AHB_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
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<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>;
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clock-names = "gcc_bus",
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"iface_clk", "branch_clk", "core_clk", "vsync_clk",
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"lut_clk";
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clock-rate = <0 0 520000000 520000000 19200000 520000000>;
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clock-max-rate = <0 0 520000000 520000000 19200000 520000000>;
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/* data and reg bus scale settings */
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interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
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<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
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<&gem_noc MASTER_APPSS_PROC
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&config_noc SLAVE_DISPLAY_CFG>;
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interconnect-names = "qcom,sde-data-bus0",
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"qcom,sde-ebi-bus", "qcom,sde-reg-bus";
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qcom,sde-ib-bw-vote = <2500000 0 800000>;
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qcom,sde-has-idle-pc;
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qcom,sde-dspp-ltm-version = <0x00010002>;
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/* offsets are based off dspp 0 and 1 */
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qcom,sde-dspp-ltm-off = <0x15300 0x14300>;
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};
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&disp_rsc_drv0 {
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sde_rsc_rpmh {
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compatible = "qcom,sde-rsc-rpmh";
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cell-index = <0>;
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};
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};
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&mdss_dsi0 {
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vdda-1p2-supply = <&L4B>;
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clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
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<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
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<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
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<&dispcc DISP_CC_MDSS_ESC0_CLK>,
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<&rpmhcc RPMH_CXO_CLK>;
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clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
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"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
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};
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&mdss_dsi_phy0 {
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vdda-0p9-supply = <&L2B>;
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qcom,panel-allow-phy-poweroff;
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qcom,dsi-pll-ssc-en;
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qcom,dsi-pll-ssc-mode = "down-spread";
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pll_codes_region = <&dsi_pll_codes_data>;
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};
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