#include <dt-bindings/clock/qcom,gcc-ravelin.h>
#include <dt-bindings/gpio/gpio.h>

&soc {
	pcie0: qcom,pcie@1c00000 {
		compatible = "qcom,pci-msm";

		reg = <0x01c00000 0x3000>,
			<0x01c06000 0x2000>,
			<0x60000000 0xf1d>,
			<0x60000f20 0xa8>,
			<0x60001000 0x1000>,
			<0x60100000 0x100000>;
		reg-names = "parf", "phy", "dm_core", "elbi", "iatu", "conf";

		cell-index = <0>;
		linux,pci-domain = <0>;

		#address-cells = <3>;
		#size-cells = <2>;
		ranges = <0x01000000 0x0 0x60200000 0x60200000 0x0 0x100000>,
			<0x02000000 0x0 0x60300000 0x60300000 0x0 0x3d00000>;

		interrupt-parent = <&pcie0>;
		interrupts = <0 1 2 3 4>;
		interrupt-names = "int_global_int", "int_a", "int_b", "int_c",
				"int_d";
		#interrupt-cells = <1>;
		interrupt-map-mask = <0 0 0 0xffffffff>;

		interrupt-map = <0 0 0 0 &intc GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH
				0 0 0 1 &intc GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH
				0 0 0 2 &intc GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH
				0 0 0 3 &intc GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH
				0 0 0 4 &intc GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>;

		msi-parent = <&pcie0_msi>;

		perst-gpio = <&tlmm 32 GPIO_ACTIVE_HIGH>;
		wake-gpio = <&tlmm 31 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pcie0_perst_default
				&pcie0_clkreq_default
				&pcie0_wake_default>;
		pinctrl-1 = <&pcie0_perst_default
				&pcie0_clkreq_sleep
				&pcie0_wake_default>;

		gdsc-vdd-supply = <&gcc_pcie_0_gdsc>;
		vreg-1p8-supply = <&L16B>;
		vreg-0p9-supply = <&L5B>;
		vreg-cx-supply = <&VDD_CX_LEVEL>;
		vreg-mx-supply = <&VDD_MX_LEVEL>;
		qcom,vreg-1p8-voltage-level = <1200000 1200000 15070>;
		qcom,vreg-0p9-voltage-level = <880000 880000 46890>;
		qcom,vreg-cx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_NOM 0>;
		qcom,vreg-mx-voltage-level = <RPMH_REGULATOR_LEVEL_MAX
						RPMH_REGULATOR_LEVEL_NOM 0>;
		qcom,bw-scale = /* Gen1 */
				<RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen2 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				19200000
				/* Gen3 */
				RPMH_REGULATOR_LEVEL_LOW_SVS
				RPMH_REGULATOR_LEVEL_LOW_SVS
				100000000>;

		interconnect-names = "icc_path";
		interconnects = <&pcie_anoc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>;

		clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_PCIE_0_AUX_CLK>,
			<&gcc GCC_PCIE_0_CFG_AHB_CLK>,
			<&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
			<&gcc GCC_PCIE_0_SLV_AXI_CLK>,
			<&gcc GCC_PCIE_0_CLKREF_EN>,
			<&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
			<&gcc GCC_PCIE_0_PHY_RCHNG_CLK>,
			<&gcc GCC_DDRSS_PCIE_SF_TBU_CLK>,
			<&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
			<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
			<&gcc GCC_PCIE_0_PIPE_CLK_SRC>,
			<&gcc GCC_PCIE_0_PIPE_DIV2_CLK>,
			<&gcc GCC_QMIP_PCIE_AHB_CLK>,
			<&pcie_0_pipe_clk>;
		clock-names = "pcie_0_pipe_clk", "pcie_0_ref_clk_src",
				"pcie_0_aux_clk", "pcie_0_cfg_ahb_clk",
				"pcie_0_mstr_axi_clk", "pcie_0_slv_axi_clk",
				"pcie_0_ldo", "pcie_0_slv_q2a_axi_clk",
				"pcie_phy_refgen_clk",
				"pcie_ddrss_sf_tbu_clk",
				"pcie_aggre_noc_0_axi_clk", "pcie_cfg_noc_pcie_anoc_ahb_clk",
				"pcie_pipe_clk_mux", "pcie_0_pipe_div2_clk",
				"pcie_qmip_pcie_ahb_clk", "pcie_pipe_clk_ext_src";
		max-clock-frequency-hz = <0>, <0>, <0>, <19200000>, <0>, <0>,
					<0>, <0>, <0>, <0>, <0>, <100000000>,
					<0>, <0>, <0>, <0>;

		resets = <&gcc GCC_PCIE_0_BCR>,
			<&gcc GCC_PCIE_0_PHY_BCR>;
		reset-names = "pcie_0_core_reset",
				"pcie_0_phy_reset";

		dma-coherent;
		qcom,smmu-sid-base = <0x1400>;
		iommu-map = <0x0 &apps_smmu 0x1400 0x1>,
			<0x100 &apps_smmu 0x1401 0x1>;

		qcom,boot-option = <0x1>;
		qcom,aux-clk-freq = <20>; /* 19.2 MHz */
		qcom,drv-supported;
		qcom,drv-l1ss-timeout-us = <5000>;
		qcom,l1-2-th-scale = <2>;
		qcom,l1-2-th-value = <150>;
		qcom,slv-addr-space-size = <0x4000000>;
		qcom,ep-latency = <10>;
		qcom,num-parf-testbus-sel = <0xb9>;
		qcom,config-recovery;

		qcom,pcie-phy-ver = <107>;
		qcom,phy-status-offset = <0x214>;
		qcom,phy-status-bit = <6>;
		qcom,phy-power-down-offset = <0x240>;
		qcom,phy-sequence = <0x0240 0x03 0x0
				0x0094 0x08 0x0
				0x0154 0x34 0x0
				0x016c 0x08 0x0
				0x0058 0x0f 0x0
				0x00a4 0x42 0x0
				0x0110 0x24 0x0
				0x011c 0x03 0x0
				0x0118 0xb4 0x0
				0x010c 0x02 0x0
				0x01bc 0x11 0x0
				0x00bc 0x82 0x0
				0x00d4 0x03 0x0
				0x00d0 0x55 0x0
				0x00cc 0x55 0x0
				0x00b0 0x1a 0x0
				0x00ac 0x0a 0x0
				0x00c4 0x68 0x0
				0x00e0 0x02 0x0
				0x00dc 0xaa 0x0
				0x00d8 0xab 0x0
				0x00b8 0x34 0x0
				0x00b4 0x14 0x0
				0x0158 0x01 0x0
				0x0074 0x06 0x0
				0x007c 0x16 0x0
				0x0084 0x36 0x0
				0x0078 0x06 0x0
				0x0080 0x16 0x0
				0x0088 0x36 0x0
				0x01b0 0x1e 0x0
				0x01ac 0xca 0x0
				0x01b8 0x18 0x0
				0x01b4 0xa2 0x0
				0x0050 0x07 0x0
				0x0010 0x01 0x0
				0x001c 0x31 0x0
				0x0020 0x01 0x0
				0x0024 0xde 0x0
				0x0028 0x07 0x0
				0x0030 0x4c 0x0
				0x0034 0x06 0x0
				0x0ee4 0x20 0x0
				0x0e84 0x75 0x0
				0x0e90 0x3f 0x0
				0x115c 0x7f 0x0
				0x1160 0xff 0x0
				0x1164 0xbf 0x0
				0x1168 0x3f 0x0
				0x116c 0xd8 0x0
				0x1170 0xdc 0x0
				0x1174 0xdc 0x0
				0x1178 0x5c 0x0
				0x117c 0x34 0x0
				0x1180 0xa6 0x0
				0x1190 0x34 0x0
				0x1194 0x38 0x0
				0x10d8 0x0f 0x0
				0x0e3c 0x12 0x0
				0x0e40 0x01 0x0
				0x10dc 0x00 0x0
				0x104c 0x08 0x0
				0x1050 0x08 0x0
				0x1044 0xf0 0x0
				0x11a4 0x38 0x0
				0x10cc 0xf0 0x0
				0x10f4 0x07 0x0
				0x1008 0x09 0x0
				0x1014 0x05 0x0
				0x0694 0x00 0x0
				0x0654 0x00 0x0
				0x06a8 0x0f 0x0
				0x0048 0x90 0x0
				0x0620 0xc1 0x0
				0x0388 0x77 0x0
				0x0398 0x0b 0x0
				0x02dc 0x05 0x0
				0x0200 0x00 0x0
				0x0244 0x03 0x0>;

		qcom,parf-debug-reg = <0x01B0 0x0024 0x0028 0x0224 0x0500
					0x04D0 0x04D4 0x03C0 0x0630 0x0230
					0x0000>;

		qcom,dbi-debug-reg = <0x0104 0x0110 0x0080 0x0204 0x0730
					0x0734 0x0738 0x073C>;

		qcom,phy-debug-reg = <0x0068 0x0140 0x0144 0x0148 0x014C
					0x0150 0x0160 0x0178 0x0ED0 0x0EDC
					0x0F34 0x0F38 0x0f3C 0x0F40 0x0F44
					0x0F48 0x0F4C 0x0F50 0x0F54 0x0F58
					0x11E8 0x0A00 0x0A04 0x0A08 0x0A0C
					0x0A10 0x0A14 0x0A18 0x0C20 0x0214
					0x0218 0x021C 0x0220 0x0224 0x0228
					0x022C 0x0230 0x0234 0x0238 0x023C
					0x0600 0x0604 0x1204 0x1210>;

		status = "disabled";
		pcie0_rp: pcie0_rp {
			reg = <0 0 0 0 0>;
		};
	};

	pcie0_msi: qcom,pcie0_msi@0x17210040 {
		compatible = "qcom,pci-msi";
		msi-controller;
		reg = <0x17210040 0x0>;
		interrupt-parent = <&intc>;
		interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 769 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 770 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 771 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 772 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 773 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 774 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 775 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 776 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 777 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 778 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 779 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 780 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 781 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 782 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 783 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 784 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 785 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 786 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 787 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 788 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 789 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 790 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 791 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 792 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 793 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 794 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 795 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 796 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 797 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 798 IRQ_TYPE_EDGE_RISING>,
			<GIC_SPI 799 IRQ_TYPE_EDGE_RISING>;
		status = "disabled";
	};
};
