#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,gcc-neo.h>
#include <dt-bindings/clock/qcom,gpucc-neo.h>
#include <dt-bindings/clock/qcom,camcc-neo.h>
#include <dt-bindings/clock/qcom,dispcc-neo.h>
#include <dt-bindings/clock/qcom,tcsrcc.h>
#include <dt-bindings/clock/qcom,videocc-neo.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,neo.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/clock/qcom,aop-qmp.h>

/ {
	model = "Qualcomm Technologies, Inc. NEO";
	compatible = "qcom,neo";
	qcom,msm-id = <525 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen: chosen {
		bootargs = " rcupdate.rcu_expedited=1 rcu_nocbs=0-7 kpti=off log_buf_len=256K pcie_ports=compat console=ttyMSM0,115200,n8 loglevel=6 cpufreq.default_governor=performance swiotlb=noforce cgroup.memory=nokmem,nosocket allow_file_spec_access msm_rtb.filter=0x237 disable_dma32=on ftrace_dump_on_oops net.ifnames=0";
	};

	memory { device_type = "memory"; reg = <0 0 0 0>; };

	reserved_memory: reserved-memory { };

	aliases: aliases {
		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/
		serial0 = &qupv3_se11_2uart;
		hsuart0 = &qupv3_se7_4uart;
	};

	firmware: firmware { };

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
				next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "arm,arch-cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@1 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_1>;
			cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			#cooling-cells = <2>;
			L2_1: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
				next-level-cache = <&L3_1>;

				L3_1: l3-cache {
					compatible = "arm,arch-cache";
					cache-level = <3>;
				};
			};
		};

		CPU2: cpu@2 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_2>;
			cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			#cooling-cells = <2>;
			L2_2: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
				next-level-cache = <&L3_2>;

				L3_2: l3-cache {
					compatible = "arm,arch-cache";
					cache-level = <3>;
				};
			};
		};

		CPU3: cpu@3 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_3>;
			cpu-idle-states = <&LITTLE_CPU_OFF &LITTLE_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			#cooling-cells = <2>;
			L2_3: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
				next-level-cache = <&L3_3>;

				L3_3: l3-cache {
					compatible = "arm,arch-cache";
					cache-level = <3>;
				};
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};
		};
	};

	idle-states {
		entry-method = "psci";

		LITTLE_CPU_OFF: silver-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <549>;
			exit-latency-us = <901>;
			min-residency-us = <1774>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		LITTLE_CPU_RAIL_OFF: silver-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <702>;
			exit-latency-us = <915>;
			min-residency-us = <4001>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_OFF: cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			idle-state-name = "l3-off";
			entry-latency-us = <2752>;
			exit-latency-us = <3048>;
			min-residency-us = <6118>;
			arm,psci-suspend-param = <0x41000044>;
		};

		CX_OFF: cx-off { /* Cx Off */
			compatible = "domain-idle-state";
			idle-state-name = "cx-off";
			entry-latency-us = <3263>;
			exit-latency-us = <4562>;
			min-residency-us = <8467>;
			arm,psci-suspend-param = <0x41002344>;
		};

		LLCC_OFF: cluster-e3 { /* E3 */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <3638>;
			exit-latency-us = <6562>;
			min-residency-us = <9826>;
			arm,psci-suspend-param = <0x4100C344>;
		};
	};

	soc: soc { };

};

&firmware {
	qcom_scm {
		compatible = "qcom,scm";
		qcom,dload-mode = <&tcsr 0x13000>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom_smcinvoke {
		compatible = "qcom,smcinvoke";
	};
};

#include "neo-reserved-memory.dtsi"

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	cdsp_eva_mem: cdsp_eva_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x400000>;
	};

	/* global autoconfigured region for contiguous allocations */
	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
		linux,cma-default;
	};

	ramoops_mem: ramoops_region {
		compatible = "ramoops";
		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
		size = <0x0 0x200000>;
		pmsg-size = <0x200000>;
		mem-type = <2>;
	};

	va_md_mem: va_md_mem_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		size = <0 0x1000000>;
	};

	user_contig_mem: user_contig_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x400000>;
	};

	qseecom_mem: qseecom_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x400000>;
	};

	qseecom_ta_mem: qseecom_ta_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x400000>;
	};

	llcc_tcm_mem: llcc_tcm_region {
		no-map;
		reg = <0x0 0x15800000 0x0 0x800000>;
	};

	adsp_mem_heap: adsp_heap_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x800000>;
	};

	lsr_lefteye_mem_heap: lsr_lefteye_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		no-map;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	lsr_righteye_mem_heap: lsr_righteye_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		no-map;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	lsr_depth_mem_heap: lsr_depth_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		no-map;
		alignment = <0x0 0x400000>;
		size = <0x0 0x100000>;
	};

	lsr_misc_mem_heap: lsr_misc_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		no-map;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2800000>;
	};

	audio_cma_mem: audio_cma_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_OFF &CX_OFF &LLCC_OFF>;
		};
	};

	slimbam: bamdma@3304000 {
		compatible = "qcom,bam-v1.7.0";
		qcom,controlled-remotely;
		reg = <0x3304000 0x20000>, <0x326b000 0x1000>;
		reg-names = "bam", "bam_remote_mem";
		num-channels  = <31>;
		interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		qcom,ee = <1>;
		qcom,num-ees = <2>;
	};

	slim_msm: slim@3340000 {
		compatible = "qcom,slim-ngd-v1.5.0";
		reg = <0x3340000 0x2C000>, <0x326a000 0x1000>;
		reg-names = "ctrl", "slimbus_remote_mem";
		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
		qcom,apps-ch-pipes = <0x0>;
		qcom,ea-pc = <0x470>;
		dmas = <&slimbam 3>, <&slimbam 4>;
		dma-names = "rx", "tx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "disabled";

		ngd@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <1>;

			/* slimbus child nodes */
			slimbus: btfmslim-driver {
				compatible = "slim217,221";
				reg = <1 0>;
			};
		};
	};

	bluetooth: bt_wcn6x5x {
		compatible = "qcom,wcn6750-bt";
		qcom,bt-reset-gpio = <&tlmm 46 0>; /* BT_EN */
		qcom,wl-reset-gpio = <&tlmm 45 0>; /* WL_EN */

		qcom,bt-vdd-io-supply = <&L15A>;  /* IO */

		/* max voltage are set to regulator max voltage supported */
		qcom,bt-vdd-io-config = <1800000 2000000 0 1>;
	};

	intc: interrupt-controller@0x17200000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17200000 0x10000>,     /* GICD */
		      <0x17260000 0x100000>;    /* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
	};

	spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc42d000 0x4000>,
		      <0xc400000 0x3000>,
		      <0xc500000 0x400000>,
		      <0xc440000 0x80000>,
		      <0xc4c0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,mid = <0>;
		qcom,bus-id = <0>;
	};

	wdog: qcom,wdt@17410000 {
		compatible = "qcom,msm-watchdog";
		reg = <0x17410000 0x1000>;
		reg-names = "wdt-base";
		interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	kryo-erp {
		compatible = "arm,arm64-kryo-cpu-erp";
		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "l1-l2-faultirq","l3-scu-faultirq";
	};

	apps_rsc: rsc@17a00000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x17a00000 0x10000>,
		      <0x17a10000 0x10000>,
		      <0x17a20000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS    3>,
				  <SLEEP_TCS     2>,
				  <WAKE_TCS      2>,
				  <CONTROL_TCS   0>, /* PDC wakeup values will be written from TZ */
				  <FAST_PATH_TCS 1>;
		power-domains = <&CLUSTER_PD>;

		apps_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
		};

		rpmhcc: qcom,rpmhclk {
			compatible = "qcom,neo-rpmh-clk";
			#clock-cells = <1>;
		};
		dcvs_fp: qcom,dcvs-fp {
			compatible = "qcom,dcvs-fp";
			qcom,ddr-bcm-name = "MC3";
			qcom,llcc-bcm-name = "SH5";
		};
	};

	cluster-device {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD>;
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <ACTIVE_TCS    0>,
				  <SLEEP_TCS     1>,
				  <WAKE_TCS      1>,
				  <CONTROL_TCS   0>,
				  <FAST_PATH_TCS 0>;

		disp_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
		};
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};
	cache_controller: cache-controller@19200000 {
		compatible = "qcom,neo-llcc", "qcom,llcc-v31";
		reg = <0x19200000 0x180000>, <0x19A00000 0x80000>,
		      <0x19AF0000 0x8000>, <0x19CF0000 0x8000>;
		reg-names = "llcc_base", "llcc_broadcast_base",
			    "spad_or_broadcast_base", "spad_and_broadcast_base";
		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;
		memory-region = <&llcc_tcm_mem>;

		llcc-perfmon {
			compatible = "qcom,llcc-perfmon";
			clocks = <&aoss_qmp QDSS_CLK>;
			clock-names = "qdss_clk";
		};

		llcc-perfmon-spad {
			compatible = "qcom,llcc-perfmon-spad";
		};
	};

	vendor_hooks: qcom,cpu-vendor-hooks {
		compatible = "qcom,cpu-vendor-hooks";
	};

	qcom,msm-imem@146aa000 {
		compatible = "qcom,msm-imem";
		reg = <0x146aa000 0x1000>;
		ranges = <0x0 0x146aa000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10  {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,pil-reloc-info";
			reg = <0x94c 0xc8>;
		};

		pil@6dc {
			compatible = "qcom,msm-imem-pil-disable-timeout";
			reg = <0x6dc 0x4>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <19200000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_1_pipe_clk: pcie_1_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,neo-gcc", "syscon";
		reg = <0x100000 0x1f4200>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
			<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
			<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
		clock-names = "bi_tcxo", "sleep_clk",
			"pcie_0_pipe_clk", "pcie_1_pipe_clk",
			"usb3_phy_wrapper_gcc_usb30_pipe_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,neo-camcc", "syscon";
		reg = <0xade0000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&sleep_clk>,
			<&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			"sleep_clk", "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc: clock-controller@af00000 {
		compatible = "qcom,neo-dispcc", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&rpmhcc RPMH_CXO_CLK_A>,
			<&sleep_clk>,
			<&gcc GCC_DISP_AHB_CLK>;
		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,neo-videocc", "syscon";
		reg = <0xaaf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&sleep_clk>,
			<&gcc GCC_VIDEO_AHB_CLK>;
		clock-names = "bi_tcxo", "sleep_clk",
			"iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,neo-gpucc", "syscon";
		reg = <0x3d90000 0xa000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_GPU_GPLL0_CLK_SRC>,
			<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo",
			"gpll0_out_main",
			"gpll0_out_main_div";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	cpufreq_hw: qcom,cpufreq-hw {
		compatible = "qcom,cpufreq-hw-epss";
		reg = <0x17d91000 0x1000>;
		reg-names = "freq-domain0";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
		clock-names = "xo", "alternate";
		qcom,lut-row-size = <4>;
		qcom,skip-enable-check;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "dcvsh0_int";
		#freq-domain-cells = <2>;
	};

	qcom,cpufreq-hw-debug {
		compatible = "qcom,cpufreq-hw-epss-debug";
		qcom,freq-hw-domain = <&cpufreq_hw 0>;
	};

	tcsrcc: clock-controller@1fc0000 {
		compatible = "qcom,tcsrcc", "syscon";
		reg = <0x1fc0000 0x30000>;
		reg-name = "cc_base";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	sdhc1_opp_table: sdhc1-opp-table {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-peak-kBps = <500000 200000>;
			opp-avg-kBps = <104000 0>;
		};

		opp-384000000 {
			opp-hz = /bits/ 64 <384000000>;
			opp-peak-kBps = <2500000 1000000>;
			opp-avg-kBps = <400000 0>;
		};
	};

	llcc_pmu: llcc-pmu@19095000 {
		compatible = "qcom,llcc-pmu-ver2";
		reg = <0x19095000 0x300>;
		reg-names = "lagg-base";
	};

	qcom_pmu: qcom,pmu {
		compatible = "qcom,pmu";
		qcom,pmu-events-tbl =
			< 0x0008 0xFF 0xFF 0xFF >,
			< 0x0011 0xFF 0xFF 0xFF >,
			< 0x0017 0xFF 0xFF 0xFF >,
			< 0x002A 0xFF 0xFF 0xFF >,
			< 0x1000 0xFF 0xFF 0xFF >;
	};

	ddr_freq_table: ddr-freq-table {
		qcom,freq-tbl =
			<  451200 >,
			<  547200 >,
			<  681600 >,
			<  768000 >,
			< 1017600 >,
			< 1555200 >,
			< 1708800 >,
			< 2092800 >,
			< 2133000 >;
	};

	llcc_freq_table: llcc-freq-table {
		qcom,freq-tbl =
			<  150000 >,
			<  300000 >,
			<  466500 >,
			<  600000 >,
			<  806000 >;
	};

	qcom_dcvs: qcom,dcvs {
		compatible = "qcom,dcvs";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qcom_l3_dcvs_hw: l3 {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <2>;
			qcom,bus-width = <32>;
			reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
			reg-names = "l3-base", "l3tbl-base";

			l3_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				qcom,shared-offset = <0x0090>;
			};
		};

		qcom_ddr_dcvs_hw: ddr {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <0>;
			qcom,bus-width = <4>;
			qcom,freq-tbl = <&ddr_freq_table>;

			ddr_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&mc_virt MASTER_LLCC
						 &mc_virt SLAVE_EBI1>;
			};

			ddr_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};

		};

		qcom_llcc_dcvs_hw: llcc {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <1>;
			qcom,bus-width = <16>;
			qcom,freq-tbl = <&llcc_freq_table>;

			llcc_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&gem_noc MASTER_APPSS_PROC
						 &gem_noc SLAVE_LLCC>;
			};

			llcc_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};

		};
	};

	qcom_memlat: qcom,memlat {
		compatible = "qcom,memlat";

		ddr {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
			qcom,sampling-path = <&ddr_dcvs_fp>;
			qcom,miss-ev = <0x1000>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					<  940800  451000 >,
					< 1113600  547000 >,
					< 1497600  768000 >,
					< 1804800 1017000 >;
				qcom,sampling-enabled;
			};

			silver-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					< 1113600  451000 >,
					< 1497600  547000 >,
					< 1804800  768000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		llcc {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
			qcom,sampling-path = <&llcc_dcvs_fp>;
			qcom,miss-ev = <0x2A>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					< 1497600  300000 >;
				qcom,sampling-enabled;
			};
		};

		l3 {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_l3_dcvs_hw>;
			qcom,sampling-path = <&l3_dcvs_sp>;
			qcom,miss-ev = <0x17>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					<  691200  556800 >,
					< 1113600  768000 >,
					< 1497600  940800 >,
					< 1804800 1190400 >,
					< 1996800 1516800 >;
				qcom,sampling-enabled;
			};
		};
	};

	bwmon_llcc: qcom,bwmon-llcc@190b6400 {
		compatible = "qcom,bwmon4";
		reg = <0x190b6400 0x300>, <0x190b6300 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
	};

	bwmon_ddr: qcom,bwmon-ddr@19091000 {
		compatible = "qcom,bwmon5";
		reg = <0x19091000 0x1000>;
		reg-names = "base";
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
	};

	crypto_node {
		compatible = "qcom,crypto";
	};

	sdhc_1: sdhci@7C4000 {
		status = "disabled";

		compatible = "qcom,sdhci-msm-v5";
		reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>,
		      <0x007C8000 0x8000>, <0x007D0000 0x9000>;
		reg-names = "hc", "cqhci", "cqhci_ice", "cqhci_ice_hwkm";

		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 222 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		bus-width = <8>;
		non-removable;
		supports-cqe;

		no-sd;
		no-sdio;

		mmc-ddr-1_8v;
		mmc-hs200-1_8v;
		mmc-hs400-1_8v;
		mmc-hs400-enhanced-strobe;

		qcom,devfreq,freq-table = <50000000 200000000>;
		qcom,scaling-lower-bus-speed-mode = "DDR52";
		qcom,need_special_up_threshold;

		qcom,dll_lock_bist_fail_wa;
		cap-mmc-hw-reset;

		iommus = <&apps_smmu 0x160 0x0>;
		dma-coherent;
		qcom,iommu-dma = "fastmap";

		clocks = <&gcc GCC_SDCC1_AHB_CLK>,
			<&gcc GCC_SDCC1_APPS_CLK>,
			<&gcc GCC_SDCC1_ICE_CORE_CLK>;
		clock-names = "iface", "core", "ice_core";

		qcom,ice-clk-rates = <300000000 100000000>;

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x000F442C 0x0 0x01
					0x090106C0 0x80040868>;

		/* Add dt entry for gcc hw reset */
		resets = <&gcc GCC_SDCC1_BCR>;
		reset-names = "core_reset";

		interconnects = <&system_noc MASTER_SDCC_1 &mc_virt SLAVE_EBI1>,
			      <&gem_noc MASTER_APPSS_PROC &config_noc
			      SLAVE_SDCC_1>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";
		operating-points-v2 = <&sdhc1_opp_table>;

		qos0 {
			mask = <0x0f>;
			vote = <44>;
		};
	};

	qcom,chd {
		compatible = "qcom,core-hang-detect";
		label = "core";
		qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058>;
		qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060>;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	dload_mode {
		compatible = "qcom,dload-mode";
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	adsp_pas: remoteproc-adsp@03000000 {
		compatible = "qcom,neo-adsp-pas";
		reg = <0x03000000 0x10000>;

		cx-supply = <&VDD_LPI_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM 0>;
		mx-supply = <&VDD_LPI_MX_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_NOM 0>;
		reg-names = "cx", "mx";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "crypto_ddr";

		memory-region = <&adsp_mem>;

		/* Inputs from ssc */
		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					<&adsp_smp2p_in 0 0>,
					<&adsp_smp2p_in 2 0>,
					<&adsp_smp2p_in 1 0>,
					<&adsp_smp2p_in 3 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		status = "ok";

		glink_edge: glink-edge {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "adsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_LPASS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
					compatible = "qcom,msm-fastrpc-rpmsg";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					qcom,intents = <0x64 64>;
			};
		};
	};

	cdsp_pas: remoteproc-cdsp@32300000 {
		compatible = "qcom,neo-cdsp-pas";
		reg = <0x32300000 0x10000>;

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-supply = <&VDD_MXC_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		nsp-supply = <&VDD_NSP_LEVEL>;
		nsp-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		reg-names = "cx","mx","nsp";
		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;
		interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
				<&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "rproc_ddr", "crypto_ddr";

		memory-region = <&cdsp_mem>;

		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					<&cdsp_smp2p_in 0 0>,
					<&cdsp_smp2p_in 2 0>,
					<&cdsp_smp2p_in 1 0>,
					<&cdsp_smp2p_in 3 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
		status = "ok";

		glink-edge {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "cdsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_CDSP
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};
			qcom,msm_fastrpc_rpmsg {
					compatible = "qcom,msm-fastrpc-rpmsg";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					qcom,intents = <0x64 64>;
			};

			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12>;

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-latency-us = <70>;
					qcom,qos-maxhold-ms = <20>;
				};
			};
		};
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-disp-bus {
			qcom,glinkpkt-edge = "helios";
			qcom,glinkpkt-ch-name = "AH_BUS";
			qcom,glinkpkt-dev-name = "glinkpkt_disp_bus";
		};

		qcom,glinkpkt-iris-bus {
			qcom,glinkpkt-edge = "helios";
			qcom,glinkpkt-ch-name = "AH_IRIS";
			qcom,glinkpkt-dev-name = "glinkpkt_iris_bus";
		};

		qcom,glinkpkt-ai-bus {
			qcom,glinkpkt-edge = "helios";
			qcom,glinkpkt-ch-name = "AH_AI";
			qcom,glinkpkt-dev-name = "glinkpkt_ai_bus";
		};

		qcom,glinkpkt-pm-bus {
			qcom,glinkpkt-edge = "helios";
			qcom,glinkpkt-ch-name = "AH_PM";
			qcom,glinkpkt-dev-name = "glinkpkt_pm_bus";
		};
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,neo-clk_virt";
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		#interconnect-cells = <1>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,neo-mc_virt";
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
		#interconnect-cells = <1>;
	};

	config_noc: interconnect@1500000 {
		reg = <0x1500000 0x10>;
		compatible = "qcom,neo-config_noc";
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		#interconnect-cells = <1>;
	};

	system_noc: interconnect@1680000 {
		reg = <0x1680000 0x29080>;
		compatible = "qcom,neo-system_noc";
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		#interconnect-cells = <1>;
		clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
	};

	pcie_noc: interconnect@16c0000 {
		reg = <0x16c0000 0xA080>;
		compatible = "qcom,neo-pcie_anoc";
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		#interconnect-cells = <1>;
		clocks =  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
			<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
	};

	mmss_noc: interconnect@1740000 {
		reg = <0x1740000 0x1F100>;
		compatible = "qcom,neo-mmss_noc";
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
		#interconnect-cells = <1>;
	};

	gem_noc: interconnect@19100000 {
		reg = <0x19100000 0xA2080>;
		compatible = "qcom,neo-gem_noc";
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
		#interconnect-cells = <1>;
	};

	apsscc: syscon@17aa0000 {
		compatible = "syscon";
		reg = <0x17aa0000 0x1c>;
	};

	mccc: syscon@190ba000 {
		compatible = "syscon";
		reg = <0x190ba000 0x54>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,neo-debugcc";
		qcom,gcc = <&gcc>;
		qcom,videocc = <&videocc>;
		qcom,camcc = <&camcc>;
		qcom,gpucc = <&gpucc>;
		qcom,dispcc = <&dispcc>;
		qcom,apsscc = <&apsscc>;
		qcom,mccc = <&mccc>;
		clock-names = "xo_clk_src",
				"gcc",
				"videocc",
				"dispcc",
				"camcc",
				"gpucc";
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc 0>,
			<&videocc 0>,
			<&dispcc 0>,
			<&camcc 0>,
			<&gpucc 0>;
		#clock-cells = <1>;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		qcom,irq-is-percpu;
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	nsp_noc: interconnect@320C0000 {
		reg = <0x320C0000 0x10>;
		compatible = "qcom,neo-nsp_noc";
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		#interconnect-cells = <1>;
	};

	lpass_ag_noc: interconnect@3c40000 {
		reg = <0x3c40000 0x10>;
		compatible = "qcom,neo-lpass_ag_noc";
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		#interconnect-cells = <1>;
	};

	mini_dump_node {
		compatible = "qcom,minidump";
	};

	va_mini_dump {
		compatible = "qcom,va-minidump";
		memory-region = <&va_md_mem>;
		status = "ok";
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	ipcc_mproc: qcom,ipcc@ed18000 {
		compatible = "qcom,ipcc";
		reg = <0xed18000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	ipcc_compute_l0: qcom,ipcc_compute_l0@408000 {
		compatible = "qcom,ipcc";
		reg = <0x408000 0x1000>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	ipclite {
		compatible = "qcom,ipclite";
		memory-region = <&global_sync_mem>;
		hwlocks = <&tcsr_mutex 11>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		ipclite_apss: apss {
			qcom,remote-pid = <0>;
			label = "apss";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
					interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_BROADCAST
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_4 {
				index = <4>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_5 {
				index = <5>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
					IRQ_TYPE_EDGE_RISING>;
			};
		};

		ipclite_cdsp: cdsp {
			qcom,remote-pid = <5>;
			label = "cdsp";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_4 {
				index = <4>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_5 {
				index = <5>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
					IRQ_TYPE_EDGE_RISING>;
			};
		};

		ipclite_cvp: cvp {
			qcom,remote-pid = <6>;
			label = "cvp";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_4 {
				index = <4>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_5 {
				index = <5>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
					IRQ_TYPE_EDGE_RISING>;
			};
		};

		ipclite_vpu: vpu {
			qcom,remote-pid = <8>;
			label = "vpu";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_4 {
				index = <4>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_SSR
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_5 {
				index = <5>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_DEBUG
					IRQ_TYPE_EDGE_RISING>;
			};
		};
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,pdc", "qcom,neo-pdc";
		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
		reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>, <126 716 12>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	cpuss-sleep-stats@17800054 {
		compatible = "qcom,cpuss-sleep-stats-v2";
		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
		    <0x17830054 0x4>, <0x17880098 0x4>, <0x178C0000 0x10000>;
		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
			  "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
			  "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
		num-cpus = <4>;
	};

	rpmh-sleep-stats@c3f0000 {
		compatible = "qcom,rpmh-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ss-name = "adsp", "adsp_island", "cdsp", "apss", "wpss";
		mboxes = <&qmp_aop 0>;
		ddr-freq-update;
	};

	subsystem-sleep-stats@c3f0000 {
		compatible = "qcom,subsystem-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ddr-freq-update;
	};

	qcom,power-state {
		compatible = "qcom,power-state";
		qcom,subsys-name = "lpass", "cdsp";
		qcom,rproc-handle = <&adsp_pas>, <&cdsp_pas>;
	};

	sys-pm-vx@c320000 {
		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-neo";
		reg = <0xc320000 0x0400>;
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
	};

	qcom_cedev: qcedev@1de0000 {
		compatible = "qcom,qcedev";
		reg = <0x1de0000 0x20000>,
			<0x1dc4000 0x28000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <1>;
		qcom,offload-ops-support;
		qcom,bam-pipe-offload-hlos-cpb-1 = <2>;
		qcom,bam-pipe-offload-hlos-cpb-2 = <3>;
		qcom,bam-pipe-offload-hlos-cpb-3 = <4>;
		qcom,bam-pipe-offload-hlos-cpb-4 = <8>;
		qcom,bam-pipe-offload-hlos-hlos = <9>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,bam-ee = <0>;
		qcom,icc_avg_bw = <9800>;
		qcom,icc_peak_bw = <9800>;
		qcom,smmu-s1-enable;
		qcom,no-clock-support;
		interconnect-names = "data_path";
		interconnects = <&system_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		iommus = <&apps_smmu 0x0080 0x0>,
			<&apps_smmu 0x0081 0x0>;
		qcom,iommu-dma = "atomic";
		dma-coherent;

		qcom_cedev_ns_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "ns_context";
			iommus = <&apps_smmu 0x0081 0x0>;
			dma-coherent;
		};

		qcom_cedev_s_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "secure_context";
			iommus = <&apps_smmu 0x0083 0x0>;
			qcom,iommu-vmid = <0x9>;
			qcom,secure-context-bank;
			dma-coherent;
		};
	};

	qcom_rng: qrng@10c3000 {
		compatible = "qcom,msm-rng";
		reg = <0x10c3000 0x1000>;
		qcom,no-qrng-config;
		qcom,no-clock-support;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
				IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-wpss {
		compatible = "qcom,smp2p";
		qcom,smem = <617>, <616>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P
			IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_WPSS IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <13>;

		wpss_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		wpss_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_1_in: qcom,smp2p-wlan-1-in {
			qcom,entry-name = "wlan";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_1_out: qcom,smp2p-wlan-1-out {
			qcom,entry-name = "wlan";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_wlan_2_in: qcom,smp2p-wlan-2-in {
			qcom,entry-name = "wlan_soc_wake";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_wlan_2_out: qcom,smp2p-wlan-2-out {
			qcom,entry-name = "wlan_soc_wake";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_wlan_3_out: qcom,smp2p-wlan-3-out {
			qcom,entry-name = "wlan_ep_power_save";
			#qcom,smem-state-cells = <1>;
		};

	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,neo-aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		#power-domain-cells = <1>;
		#clock-cells = <0>;
	};

	qmp_aop: qcom,qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qmp_tme: qcom,qmp-tme {
		compatible = "qcom,qmp-mbox";
		qcom,remote-pid = <14>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "tme_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;
		label = "tme";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	qcom,tmecom-qmp-client {
		compatible = "qcom,tmecom-qmp-client";
		mboxes = <&qmp_tme 0>;
		mbox-names = "tmecom";
		label = "tmecom";
		depends-on-supply = <&qmp_tme>;
	};

	qcom,secure-buffer {
		compatible = "qcom,secure-buffer";
		qcom,vmid-cp-camera-preview-ro;
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
		qcom,rproc-handle = <&cdsp_pas>;
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem_heap>;
		restrict-access;
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	msm_fastrpc: qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,adsp-remoteheap-vmid = <22 37>;
		qcom,fastrpc-adsp-audio-pdr;
		qcom,fastrpc-adsp-sensors-pdr;
		qcom,rpc-latency-us = <235>;
		qcom,fastrpc-gids = <2908>;
		qcom,qos-cores = <0 1 2 3>;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1001 0x0420>,
					 <&apps_smmu 0x1021 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1002 0x0420>,
					 <&apps_smmu 0x1022 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1003 0x0420>,
					 <&apps_smmu 0x1023 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1004 0x0420>,
					 <&apps_smmu 0x1024 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1005 0x0420>,
					 <&apps_smmu 0x1025 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1006 0x0420>,
					 <&apps_smmu 0x1026 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1007 0x0420>,
					 <&apps_smmu 0x1027 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x1008 0x0420>,
					 <&apps_smmu 0x1028 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x1009 0x0420>,
					 <&apps_smmu 0x1029 0x0420>;
			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1803 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1804 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1805 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
			shared-cb = <5>;
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1806 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};
	};

	qcom,mem-buf-msgq {
		compatible = "qcom,mem-buf-msgq";
	};

	qcom,mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "supplier";
		qcom,vmid = <3>;
	};

	thermal_zones: thermal-zones {
	};

	logbuf: qcom,logbuf-vendor-hooks {
		compatible = "qcom,logbuf-vendor-hooks";
	};

	qfprom: qfprom@221c8000 {
		compatible = "qcom,qfprom";
		reg = <0x221c8000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		read-only;
		ranges;

		gpu_speed_bin: gpu_speed_bin@119 {
			reg = <0x119 0x2>;
			bits = <5 8>;
		};
	};

	qfprom_sys: qfprom@0 {
		compatible = "qcom,qfprom-sys";

		nvmem-cells = <&gpu_speed_bin>;
		nvmem-cell-names = "gpu_speed_bin";
	};

	eud: qcom,msm-eud@88e0000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupt-parent = <&pdc>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x088e0000 0x2000>,
			<0x088e2000 0x1000>;
		reg-names = "eud_base", "eud_mode_mgr2";
		qcom,secure-eud-en;
		status = "ok";
	};

	qcom_tzlog: tz-log@146AA720 {
		compatible = "qcom,tz-log";
		reg = <0x146AA720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
		tmecrashdump-address-offset = <0x808a0000>;
	};

	qcom_qseecom: qseecom@E8900000 {
		compatible = "qcom,qseecom";
		memory-region = <&qseecom_mem>;
		qseecom_mem = <&qseecom_mem>;
		qseecom_ta_mem = <&qseecom_ta_mem>;
		user_contig_mem = <&user_contig_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,no-clock-support;
		qcom,appsbl-qseecom-support;
		qcom,commonlib64-loaded-by-uefi;
		qcom,qsee-reentrancy-support = <2>;
	};
};

#include "neo-pinctrl.dtsi"
#include "neo-coresight.dtsi"
#include "neo-debug.dtsi"
#include "neo-dma-heaps.dtsi"
#include "diwali-gdsc.dtsi"
#include "msm-arm-smmu-neo.dtsi"
#include "ipcc-test.dtsi"
#include "neo-qupv3.dtsi"
#include "neo-gpu.dtsi"

&gcc_apcs_gdsc_vote_ctrl {
	reg = <0x162200 0x4>;
};

&gcc_usb30_prim_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	qcom,support-hw-trigger;
	status = "ok";
};

&gcc_usb3_phy_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	reg = <0x18d204 0x4>;
	status = "ok";
};

&gcc_pcie_0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
	/delete-property/ qcom,support-hw-trigger;
	qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 0>;
};

&gcc_pcie_0_phy_gdsc {
	parent-supply = <&VDD_MXA_LEVEL>;
	status = "ok";
	qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 3>;
};

&gcc_pcie_1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
	qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 1>;
};

&gcc_pcie_1_phy_gdsc {
	parent-supply = <&VDD_MXA_LEVEL>;
	status = "ok";
	qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 4>;
};

&cam_cc_bps_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf0004 0x4>;
	status = "ok";
};

&cam_cc_ife_0_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf1004 0x4>;
	status = "ok";
};

&cam_cc_ife_1_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf2004 0x4>;
	status = "ok";
};

&cam_cc_ipe_0_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf03b8 0x4>;
	status = "ok";
};

&cam_cc_titan_top_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf4000 0x4>;
	status = "ok";
};

&disp_cc_mdss_core_gdsc {
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	status = "ok";
};

&disp_cc_mdss_core_int2_gdsc {
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_LEVEL>;
	status = "ok";
};

&gpu_cc_cx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_cc_gx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	clocks-names = "ahb_clk";
	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
	status = "ok";
};

&video_cc_mvs0_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xaaf80a4 0x4>;
	status = "ok";
};

&video_cc_mvs0c_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xaaf804c 0x4>;
	status = "ok";
};

&video_cc_mvs1_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xaaf80cc 0x4>;
	status = "ok";
};

&video_cc_mvs1c_gdsc {
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xaaf8078 0x4>;
	status = "ok";

};

&qupv3_se11_2uart {
	status = "ok";
};

&qupv3_se7_4uart {
	status = "ok";
};

#include "neo-usb.dtsi"
#include "neo-thermal.dtsi"
#include "helios.dtsi"
#include "neo-regulators.dtsi"
#include "neo-pcie.dtsi"
#include "msm-rdbg.dtsi"

&qupv3_se8_i2c {
	status = "ok";

	#address-cells = <1>;
	#size-cells = <0>;

	nxp_eusb2_repeater: eusb2_repeater@4f {
		compatible = "nxp,eusb2-repeater";
		reg = <0x4f>;
		vdd18-supply = <&L15A>;
		vdd3-supply = <&L2A>;
		reset-gpio = <&tlmm 99 GPIO_ACTIVE_HIGH>;
		pinctrl-names = "default";
		pinctrl-0 = <&eusb2_reset_ctrl_default>;
	};
};

&eusb2_phy0 {
	dummy-supply = <&nxp_eusb2_repeater>;
	usb-repeater = <&nxp_eusb2_repeater>;
};

&apps_rsc {
	rpmh-regulator-gfxlvl {
		compatible = "qcom,rpmh-arc-regulator";
		qcom,resource-name = "gfx.lvl";
		VDD_GFX_LEVEL: S2A_LEVEL:
		pm8150_s2_level: regulator-pm8150-s2-level {
			regulator-name = "pm8150_s2_level";
			qcom,set = <RPMH_REGULATOR_SET_ALL>;
			regulator-min-microvolt =
				<RPMH_REGULATOR_LEVEL_RETENTION>;
			regulator-max-microvolt =
				<RPMH_REGULATOR_LEVEL_MAX>;
			qcom,init-voltage-level =
				<RPMH_REGULATOR_LEVEL_RETENTION>;
		};
	};
};
