#include <dt-bindings/clock/qcom,gcc-diwali.h>
#include <dt-bindings/gpio/gpio.h>

&soc {
	timer {
		clock-frequency = <500000>;
	};

	timer@17420000 {
		clock-frequency = <500000>;
	};

	qcom,wdt@17410000 {
		status = "disabled";
	};

	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};

	usb_emuphy: phy@a784000 {
		compatible = "qcom,usb-emu-phy";
		reg = <0x0a784000 0x9500>;

		qcom,emu-init-seq = <0xfffff 0x4
		     0xffff0 0x4
		     0x100000 0x20
		     0x0 0x20
		     0x000101F0 0x20
		     0x00100000 0x3c
		     0x0 0x3c
		     0x0 0x4>;
	};

	bi_tcxo: bi_tcxo {
		compatible = "fixed-factor-clock";
		clock-mult = <1>;
		clock-div = <4>;
		clocks = <&xo_board>;
		#clock-cells = <0>;
	};

	bi_tcxo_ao: bi_tcxo_ao {
		compatible = "fixed-factor-clock";
		clock-mult = <1>;
		clock-div = <4>;
		clocks = <&xo_board>;
		#clock-cells = <0>;
	};
};

&sdhc_2 {
	status = "ok";
	vdd-supply = <&L9C>;
	qcom,vdd-voltage-level = <2960000 2960000>;
	qcom,vdd-current-level = <0 800000>;

	vdd-io-supply = <&L6C>;
	qcom,vdd-io-voltage-level = <2960000 2960000>;
	qcom,vdd-io-current-level = <0 22000>;

	cap-sd-highspeed;
	max-frequency = <100000000>;

	pinctrl-names = "default", "sleep";
	pinctrl-0 = <&sdc2_on>;
	pinctrl-1 = <&sdc2_off>;

	cd-gpios = <&tlmm 19 GPIO_ACTIVE_LOW>;
};

&gcc {
	clocks = <&bi_tcxo>, <&sleep_clk>,
		<&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>,
		<&ufs_phy_rx_symbol_1_clk>, <&ufs_phy_tx_symbol_0_clk>,
		<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
};

&LITTLE_CPU_OFF {
	status = "nok";
};

&LITTLE_CPU_RAIL_OFF {
	status = "nok";
};

&BIG_CPU_OFF {
	status = "nok";
};

&BIG_CPU_RAIL_OFF {
	status = "nok";
};

&CLUSTER_OFF {
	status = "nok";
};

&CX_RET {
	status = "nok";
};

&APSS_OFF {
	status = "nok";
};

&usb0 {
	dwc3@a600000 {
		usb-phy = <&usb_emuphy>, <&usb_nop_phy>;
		dr_mode = "peripheral";
		maximum-speed = "high-speed";
	};
};

&gpucc {
	clocks = <&bi_tcxo>,
		<&gcc GCC_GPU_GPLL0_CLK_SRC>,
		<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
};

&camcc {
	clocks = <&bi_tcxo>,
		<&bi_tcxo_ao>,
		<&sleep_clk>,
		<&gcc GCC_CAMERA_AHB_CLK>;
};

/* Debug UART Console */
&qupv3_se5_2uart {
	qcom,rumi_platform;
};

&videocc {
	clocks = <&bi_tcxo>,
		<&bi_tcxo_ao>,
		<&sleep_clk>,
		<&gcc GCC_VIDEO_AHB_CLK>;
};

&ufsphy_mem {
	compatible = "qcom,ufs-phy-qrbtc-sdm845";

	vdda-phy-supply = <&L10C>;
	vdda-pll-supply = <&L6B>;
	vdda-phy-max-microamp = <85800>;
	vdda-pll-max-microamp = <18300>;

	status = "ok";
};

&ufshc_mem {
	limit-tx-hs-gear = <1>;
	limit-rx-hs-gear = <1>;
	limit-rate = <2>; /* HS Rate-B */

	vdd-hba-supply = <&gcc_ufs_phy_gdsc>;
	vdd-hba-fixed-regulator;

	vcc-supply = <&L7B>;
	vcc-max-microamp = <800000>;

	vccq-supply = <&L9B>;
	vccq-max-microamp = <750000>;

	vccq2-supply = <&L19B>;
	vccq2-max-microamp = <750000>;

	qcom,vddp-ref-clk-supply = <&L9B>;
	qcom,vddp-ref-clk-max-microamp = <100>;

	qcom,disable-lpm;
	rpm-level = <0>;
	spm-level = <0>;

	qcom,iommu-dma = "bypass";

	status = "ok";
};

&tsens0 {
	status = "disabled";
};

&tsens1 {
	status = "disabled";
};

&rpmhcc {
	compatible = "qcom,dummycc";
	clock-output-names = "rpmhcc_clocks";
};

&dispcc {
	clocks = <&bi_tcxo>,
		<&bi_tcxo_ao>,
		<&sleep_clk>,
		<&gcc GCC_DISP_AHB_CLK>;
};

&cpufreq_hw {
	clocks = <&bi_tcxo>, <&gcc GCC_GPLL0>;
};

&debugcc {
	clocks = <&bi_tcxo>;
};
