#include <dt-bindings/clock/qcom,aop-qmp.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,waipio.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/clock/qcom,gcc-waipio.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/gpio/gpio.h>
/ {
	model = "Qualcomm Technologies, Inc. Cape";
	compatible = "qcom,cape";
	qcom,msm-id = <530 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;

	chosen: chosen {
		bootargs = "console=ttyMSM0,115200n8 loglevel=6 kpti=0 kernel.panic_on_rcu_stall=1 swiotlb=noforce loop.max_part=7 cgroup.memory=nokmem,nosocket pcie_ports=compat msm_rtb.filter=0x237 allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-7 ftrace_dump_on_oops pstore.compress=none cpufreq.default_governor=performance can.stats_timer=0 fsa4480_i2c.async_probe=1 slub_debug=- disable_dma32=on";
		stdout-path = "/soc/qcom,qup_uart@99c000:115200n8";
	};

	memory { device_type = "memory"; reg = <0 0 0 0>; };

	ddr-regions { };

	reserved_memory: reserved-memory { };

	aliases: aliases {
		serial0 = &qupv3_se7_2uart;
		hsuart0 = &qupv3_se20_4uart;
		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
		mmc1 = &sdhc_2; /* SDC2 SD card slot */
		i2c0 = &qupv3_se5_i2c;
		i2c1 = &qupv3_se9_i2c;
		i2c2 = &qupv3_se15_i2c;
		i2c3 = &qupv3_se16_i2c;
		i2c4 = &qupv3_se19_i2c;
		i2c5 = &qupv3_se17_i2c;
	};

	sram: sram@17D09400 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "mmio-sram";
		reg = <0x0 0x17D09400 0x0 0x400>;
		ranges = <0x0 0x0 0x0 0x17D09400 0x0 0x400>;

		cpu_scp_lpri: scp-shmem@0 {
			compatible = "arm,scp-shmem";
			reg = <0x0 0x0 0x0 0x400>;
		};
	};


	firmware: firmware { };

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			cpu-idle-states = <&SILVER_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			#cooling-cells = <2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "arm,arch-cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			next-level-cache = <&L2_0>; /* silver L2 sharing */
			cpu-idle-states = <&SILVER_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0 4>;
		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			enable-method = "psci";
			next-level-cache = <&L2_2>;
			cpu-idle-states = <&SILVER_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0 4>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			enable-method = "psci";
			next-level-cache = <&L2_2>; /* silver L2 sharing */
			cpu-idle-states = <&SILVER_OFF>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 0 4>;
		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			enable-method = "psci";
			next-level-cache = <&L2_4>;
			cpu-idle-states = <&GOLD_OFF>;
			capacity-dmips-mhz = <2253>;
			dynamic-power-coefficient = <257>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			#cooling-cells = <2>;
			L2_4: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			enable-method = "psci";
			next-level-cache = <&L2_5>;
			cpu-idle-states = <&GOLD_OFF>;
			capacity-dmips-mhz = <2253>;
			dynamic-power-coefficient = <257>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_5: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU6: cpu@600 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x600>;
			enable-method = "psci";
			next-level-cache = <&L2_6>;
			cpu-idle-states = <&GOLD_OFF>;
			capacity-dmips-mhz = <2253>;
			dynamic-power-coefficient = <257>;
			power-domains = <&CPU_PD6>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_6: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU7: cpu@700 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x700>;
			enable-method = "psci";
			next-level-cache = <&L2_7>;
			cpu-idle-states = <&GOLD_OFF>;
			capacity-dmips-mhz = <2386>;
			dynamic-power-coefficient = <509>;
			power-domains = <&CPU_PD7>;
			power-domain-names = "psci";
			qcom,freq-domain = <&cpufreq_hw 2 4>;
			#cooling-cells = <2>;
			L2_7: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};

				core2 {
					cpu = <&CPU2>;
				};

				core3 {
					cpu = <&CPU3>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU4>;
				};

				core1 {
					cpu = <&CPU5>;
				};

				core2 {
					cpu = <&CPU6>;
				};
			};

			cluster2 {
				core0 {
					cpu = <&CPU7>;
				};
			};
		};
	};

	idle-states {
		SILVER_OFF: silver-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <800>;
			exit-latency-us = <750>;
			min-residency-us = <4090>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_OFF: gold-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <600>;
			exit-latency-us = <1550>;
			min-residency-us = <4791>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_PWR_DN: cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			idle-state-name = "l3-off";
			entry-latency-us = <1050>;
			exit-latency-us = <2500>;
			min-residency-us = <5309>;
			arm,psci-suspend-param = <0x41000044>;
		};

		APSS_OFF: cluster-e3 { /* E3 */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <2700>;
			exit-latency-us = <3500>;
			min-residency-us = <13959>;
			arm,psci-suspend-param = <0x4100c344>;
		};
	};

	cluster-device {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD>;
	};

	soc: soc { };
};

&firmware {
	qcom_scm {
		compatible = "qcom,scm";
		qcom,dload-mode = <&tcsr 0x13000>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom_smcinvoke {
		compatible = "qcom,smcinvoke";
	};

	android {
		compatible = "android,firmware";
		vbmeta {
			compatible = "android,vbmeta";
			parts = "vbmeta,boot,system,vendor,dtbo,recovery";
		};

		fstab {
			compatible = "android,fstab";
			vendor {
				compatible = "android,vendor";
				dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
				type = "ext4";
				mnt_flags = "ro,barrier=1,discard";
				fsmgr_flags = "wait,slotselect,avb";
				status = "ok";
			};
		};
	};
};

#include "cape-reserved-memory.dtsi"

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* global autoconfigured region for contiguous allocations */
	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
		linux,cma-default;
	};

	va_md_mem: va_md_mem_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
		reusable;
		size = <0 0x1000000>;
	};

	user_contig_mem: user_contig_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	qseecom_mem: qseecom_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1400000>;
	};

	non_secure_display_memory: non_secure_display_region {
		compatible = "shared-dma-pool";
		reusable;
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		size = <0x0 0xa400000>;
		alignment = <0x0 0x400000>;
	};

	demura_heap_memory: demura_heap_region {
		compatible = "shared-dma-pool";
		reusable;
		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
		size = <0x0 0x2800000>;
		alignment = <0x0 0x400000>;
	};

	qseecom_ta_mem: qseecom_ta_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	cnss_wlan_mem: cnss_wlan_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
	};

	audio_cma_mem: audio_cma_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1C00000>;
	};

	adsp_mem_heap: adsp_heap_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xC00000>;
	};

	sdsp_mem: sdsp_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x800000>;
	};

	cdsp_eva_mem: cdsp_eva_region {
			compatible = "shared-dma-pool";
			alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
			reusable;
			alignment = <0x0 0x400000>;
			size = <0x0 0x400000>;
	};

	ramoops_mem: ramoops_region {
		compatible = "ramoops";
		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
		mem-type = <2>;
	};
};

#include "waipio-clock.dtsi"

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD4: cpu-pd4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD5: cpu-pd5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD6: cpu-pd6 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD7: cpu-pd7 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
		};
	};

	slimbam: bamdma@3304000 {
		compatible = "qcom,bam-v1.7.0";
		qcom,controlled-remotely;
		reg = <0x3304000 0x20000>, <0x326b000 0x1000>;
		reg-names = "bam", "bam_remote_mem";
		num-channels  = <31>;
		interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		qcom,ee = <1>;
		qcom,num-ees = <2>;
	};

	slim_msm: slim@3340000 {
		compatible = "qcom,slim-ngd-v1.5.0";
		reg = <0x3340000 0x2C000>, <0x326a000 0x1000>;
		reg-names = "ctrl", "slimbus_remote_mem";
		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
		qcom,apps-ch-pipes = <0x0>;
		qcom,ea-pc = <0x450>;
		dmas = <&slimbam 3>, <&slimbam 4>;
		dma-names = "rx", "tx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "ok";
		ngd@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <1>;

			/* slimbus child nodes */
			slimbus: btfmslim-driver {
				compatible = "slim217,221";
				reg = <1 0>;
			};
		};
	};

	bluetooth: bt_qca6490 {
		compatible = "qcom,qca6490";
		pinctrl-names = "default";
		pinctrl-0 = <&bt_en_sleep>;
		qcom,wl-reset-gpio = <&tlmm 80 0>; /* WL_CTRL */
		qcom,bt-reset-gpio = <&tlmm 81 0>; /* BT_EN */
		qcom,bt-sw-ctrl-gpio = <&tlmm 82 0>; /* SW_CTRL */
		qcom,xo-clk-gpio = <&tlmm 204 0>; /* XO */

		qcom,bt-vdd-io-supply = <&S10B>;  /* IO */
		qcom,bt-vdd-aon-supply = <&S11B>;
		qcom,bt-vdd-dig-supply = <&S11B>; /* BT_CX_MX */
		qcom,bt-vdd-rfacmn-supply = <&S11B>;
		qcom,bt-vdd-rfa-0p8-supply = <&S11B>;
		qcom,bt-vdd-rfa1-supply = <&S1C>; /* RFA 1p7 */
		qcom,bt-vdd-rfa2-supply = <&S12B>; /* RFA 1p2 */
		qcom,bt-vdd-asd-supply = <&L7E>;

		/* Max Voltages are derived from the buck Max Voltage */
		qcom,bt-vdd-io-config = <1800000 1800000 0 1>;
		qcom,bt-vdd-aon-config = <966000 1170000 0 1>;
		qcom,bt-vdd-dig-config = <966000 1170000 0 1>;
		qcom,bt-vdd-rfacmn-config  = <966000 1170000 0 1>;
		qcom,bt-vdd-rfa-0p8-config  = <966000 1170000 0 1>;
		qcom,bt-vdd-rfa1-config = <1900000 2040000 0 1>;
		qcom,bt-vdd-rfa2-config = <1350000 2024000 0 1>;
		qcom,bt-vdd-asd-config = <2800000 2800000 0 1>;
	};

	intc: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		ranges;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,	/* GICD */
		      <0x17180000 0x200000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;

		gic_its: msi-controller@17140000 {
			compatible = "arm,gic-v3-its";
			msi-controller;
			#msi-cells = <1>;
			reg = <0x17140000 0x20000>;
		};
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,cape-pinctrl";
		reg = <0x0F000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
		qcom,gpios-reserved = <28 29 30 31 36 37 38 39>;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	apps_rsc: rsc@17a00000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x17a00000 0x10000>,
		      <0x17a10000 0x10000>,
		      <0x17a20000 0x10000>,
		      <0x17a30000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			     /* No interrupt into GIC for DRV3 */
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS    3>,
				  <SLEEP_TCS     2>,
				  <WAKE_TCS      2>,
				  <CONTROL_TCS   0>, /* PDC wakeup values will be written from TZ */
				  <FAST_PATH_TCS 1>;
		power-domains = <&CLUSTER_PD>;

		clock_rpmh: qcom,rpmhclk {
			compatible = "qcom,waipio-rpmh-clk";
			#clock-cells = <1>;
		};

		apps_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
		};

		dcvs_fp: qcom,dcvs-fp {
			compatible = "qcom,dcvs-fp";
			qcom,ddr-bcm-name = "MC3";
			qcom,llcc-bcm-name = "SH5";
		 };
	};

	cpuss-sleep-stats@17800054 {
		compatible = "qcom,cpuss-sleep-stats";
		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
		      <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
		      <0x17860054 0x4>, <0x17870054 0x4>, <0x178A0098 0x4>,
		      <0x178C0000 0x10000>;
		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
			    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
			    "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
			    "seq_lpm_cntr_cfg_cpu6", "seq_lpm_cntr_cfg_cpu7",
			    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
		num-cpus = <8>;
	};

	disp_rsc: rsc@af20000 {
		label = "disp_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		clocks = <&clock_dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <ACTIVE_TCS    0>,
				  <SLEEP_TCS     1>,
				  <WAKE_TCS      1>,
				  <CONTROL_TCS   0>,
				  <FAST_PATH_TCS 0>;

		disp_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
		};
	};

	llcc_pmu: llcc-pmu@19095000 {
		compatible = "qcom,llcc-pmu-ver2";
		reg = <0x19095000 0x300>;
		reg-names = "lagg-base";
	};

	qcom_pmu: qcom,pmu {
		compatible = "qcom,pmu";
		qcom,long-counter;
		qcom,pmu-events-tbl =
			< 0x0008 0xFF 0x02 0xFF >,
			< 0x0011 0xFF 0x01 0xFF >,
			< 0x0017 0xFF 0xFF 0xFF >,
			< 0x0037 0xFF 0xFF 0xFF >,
			< 0x1000 0xFF 0xFF 0xFF >;
	};

	ddr_freq_table: ddr-freq-table {
		qcom,freq-tbl =
			<  547000 >,
			<  768000 >,
			< 1555000 >,
			< 1708000 >,
			< 2092000 >,
			< 2736000 >,
			< 3196000 >;
	};

	llcc_freq_table: llcc-freq-table {
		qcom,freq-tbl =
			<  300000 >,
			<  466000 >,
			<  600000 >,
			<  806000 >,
			<  933000 >,
			< 1066000 >;
	};

	ddrqos_freq_table: ddrqos-freq-table {
		qcom,freq-tbl =
			< 0 >,
			< 1 >;
	};

	qcom_dcvs: qcom,dcvs {
		compatible = "qcom,dcvs";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qcom_l3_dcvs_hw: l3 {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <2>;
			qcom,bus-width = <32>;
			reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
			reg-names = "l3-base", "l3tbl-base";

			l3_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				qcom,shared-offset = <0x0090>;
			};
		};

		qcom_ddr_dcvs_hw: ddr {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <0>;
			qcom,bus-width = <4>;
			qcom,freq-tbl = <&ddr_freq_table>;

		ddr_dcvs_sp: sp {
			compatible = "qcom,dcvs-path";
			qcom,dcvs-path-type = <0>;
			interconnects = <&mc_virt MASTER_LLCC
					&mc_virt SLAVE_EBI1>;
			};

			ddr_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};
		};

		qcom_llcc_dcvs_hw: llcc {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <1>;
			qcom,bus-width = <16>;
			qcom,freq-tbl = <&llcc_freq_table>;

			llcc_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&gem_noc MASTER_APPSS_PROC
						 &gem_noc SLAVE_LLCC>;
			};

			llcc_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};
		};

		qcom_ddrqos_dcvs_hw: ddrqos {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <3>;
			qcom,bus-width = <1>;
			qcom,freq-tbl = <&ddrqos_freq_table>;

			ddrqos_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&mc_virt MASTER_LLCC
						 &mc_virt SLAVE_EBI1>;
			};
		};
	};

	qcom_memlat: qcom,memlat {
		compatible = "qcom,memlat";

		ddr {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
			qcom,sampling-path = <&ddr_dcvs_fp>;
			qcom,miss-ev = <0x1000>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					< 1132800  547000 >,
					< 1440000  768000 >,
					< 1670400 1555000 >;
				qcom,sampling-enabled;
			};

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
				qcom,cpufreq-memfreq-tbl =
					<  883200  547000 >,
					< 1113600  768000 >,
					< 1324800 1555000 >,
					< 1881600 2092000 >,
					< 2457600 2736000 >,
					< 2995200 3196000 >;
				qcom,sampling-enabled;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					<  787200  547000 >,
					< 1036800  768000 >,
					< 1286400 1555000 >,
					< 1881600 2092000 >,
					< 2592000 2736000 >,
					< 2995200 3196000 >;
				qcom,sampling-enabled;
			};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1881600  547000 >,
					< 2995200 1555000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};

			prime-latfloor {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 2592000  547000 >,
					< 2995200 3196000 >;
				qcom,sampling-enabled;
			};
		};

		llcc {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
			qcom,sampling-path = <&llcc_dcvs_fp>;
			qcom,miss-ev = <0x37>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					<  556800  300000 >,
					< 1440000  466000 >,
					< 1804800  600000 >;
				qcom,sampling-enabled;
			};

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					<  633600  300000 >,
					< 1113600  466000 >,
					< 1324800  600000 >,
					< 1881600  806000 >,
					< 2572800  933000 >,
					< 2995200 1066000 >;
				qcom,sampling-enabled;
			};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1881600  300000 >,
					< 2995200  600000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		l3 {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_l3_dcvs_hw>;
			qcom,sampling-path = <&l3_dcvs_sp>;
			qcom,miss-ev = <0x17>;

			silver {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1 &CPU2 &CPU3>;
				qcom,cpufreq-memfreq-tbl =
					<  307200  307200 >,
					<  441600  403200 >,
					<  556800  518400 >,
					<  691200  710400 >,
					<  806400  806400 >,
					<  940800  902400 >,
					< 1056000  998400 >,
					< 1132800 1075200 >,
					< 1324800 1267200 >,
					< 1440000 1478400 >,
					< 1555200 1593600 >,
					< 1670400 1708800 >,
					< 1920000 1804000 >;
				qcom,sampling-enabled;
			};

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU4 &CPU5 &CPU6>;
				qcom,cpufreq-memfreq-tbl =
					<  633600  518400 >,
					<  883200  614400 >,
					< 1113600  902400 >,
					< 1324800  998400 >,
					< 1651200 1267200 >,
					< 1996800 1478400 >,
					< 2457600 1593600 >,
					< 2572800 1708800 >,
					< 2649600 1804000 >;
				qcom,sampling-enabled;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					<  787200  518400 >,
					<  921600  614400 >,
					< 1171200  902400 >,
					< 1401600  998400 >,
					< 1651200 1267200 >,
					< 1996800 1478400 >,
					< 2476800 1593600 >,
					< 2822400 1708800 >,
					< 2918400 1804000 >;
				qcom,sampling-enabled;
			};

			prime-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1996800  307200 >,
					< 2995200 1708800 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		ddrqos {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
			qcom,sampling-path = <&ddrqos_dcvs_sp>;
			qcom,miss-ev = <0x1000>;

			ddrqos_gold_lat: gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU4 &CPU5 &CPU6 &CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1881600 0 >,
					< 2822400 1 >;
				qcom,sampling-enabled;
			};

			ddrqos_prime_latfloor: prime-latfloor {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU7>;
				qcom,cpufreq-memfreq-tbl =
					< 1996800 0 >,
					< 2822400 1 >;
				qcom,sampling-enabled;
			};
		};
	};

	bwmon_llcc: qcom,bwmon-llcc@190b6400 {
		compatible = "qcom,bwmon4";
		reg = <0x190b6400 0x300>, <0x190b6300 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
	};

	bwmon_ddr: qcom,bwmon-ddr@19091000 {
		compatible = "qcom,bwmon5";
		reg = <0x19091000 0x1000>;
		reg-names = "base";
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
	};

	qrtr-gunyah {
		compatible = "qcom,qrtr-gunyah";
		qcom,master;
		gunyah-label = <3>;
		peer-name = <2>;
		shared-buffer = <&trust_ui_vm_qrtr>;
	};

	trust_ui_vm: qcom,trust_ui_vm@e55fc000 {
		reg = <0xe55fc000 0x104000>;
		vm_name = "trustedvm";
		shared-buffers = <&trust_ui_vm_vblk0_ring &trust_ui_vm_swiotlb>;
	};

	qcom,virtio_backend@0 {
		compatible = "qcom,virtio_backend";
		qcom,vm = <&trust_ui_vm>;
		qcom,label = <0x11>;
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,pdc", "qcom,cape-pdc";
		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
		reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>,
				  <126 716 12>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	qcom_tzlog: tz-log@146AA720 {
		compatible = "qcom,tz-log";
		reg = <0x146AA720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	qcom_qseecom: qseecom@c1700000 {
		compatible = "qcom,qseecom";
		memory-region = <&qseecom_mem>;
		qseecom_mem = <&qseecom_mem>;
		qseecom_ta_mem = <&qseecom_ta_mem>;
		user_contig_mem = <&user_contig_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,no-clock-support;
		qcom,appsbl-qseecom-support;
		qcom,commonlib64-loaded-by-uefi;
		qcom,qsee-reentrancy-support = <2>;
	};

	qcom_cedev: qcedev@1de0000 {
		compatible = "qcom,qcedev";
		reg = <0x1de0000 0x20000>,
			<0x1dc4000 0x24000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <2>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,bam-ee = <0>;
		qcom,smmu-s1-enable;
		qcom,no-clock-support;
		interconnect-names = "data_path";
		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		iommus = <&apps_smmu 0x0584 0x0011>;
		qcom,iommu-dma = "atomic";
		dma-coherent;

		qcom_cedev_ns_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "ns_context";
			iommus = <&apps_smmu 0x588 0x0>,
				<&apps_smmu 0x59A 0x0>,
				<&apps_smmu 0x59F 0x0>,
				<&apps_smmu 0x598 0x5>;
			dma-coherent;
		};

		qcom_cedev_s_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "secure_context";
			iommus = <&apps_smmu 0x592 0x0>,
				 <&apps_smmu 0x597 0x0>,
				 <&apps_smmu 0x59B 0x0>,
				 <&apps_smmu 0x59E 0x0>;
			qcom,iommu-vmid = <0x9>;
			qcom,secure-context-bank;
		};
	};

	qcom_rng: qrng@10c3000 {
		compatible = "qcom,msm-rng";
		reg = <0x10c3000 0x1000>;
		qcom,no-qrng-config;
		qcom,no-clock-support;
	};

	thermal_zones: thermal-zones {
	};

	qcom,mem-buf-msgq {
		compatible = "qcom,mem-buf-msgq";
	};

	qcom,mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "supplier";
		qcom,vmid = <3>;
	};

	spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc42d000 0x4000>,
		      <0xc400000 0x3000>,
		      <0xc500000 0x400000>,
		      <0xc440000 0x80000>,
		      <0xc4c0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <0>;
	};

	spmi1_bus: qcom,spmi@c432000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc432000 0x4000>,
		      <0xc400000 0x3000>,
		      <0xc500000 0x400000>,
		      <0xc440000 0x80000>,
		      <0xc4d0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <1>;
		depends-on-supply = <&spmi0_bus>;
	};

	spmi0_debug_bus: qcom,spmi-debug@10b14000 {
		compatible = "qcom,spmi-pmic-arb-debug";
		reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
		reg-names = "core", "fuse";
		clocks = <&aoss_qmp>;
		clock-names = "core_clk";
		qcom,fuse-enable-bit = <18>;
		#address-cells = <2>;
		#size-cells = <0>;
		depends-on-supply = <&spmi1_bus>;
		depends-on2-supply = <&smb1394_glink_debug>;

		qcom,pmk8350-debug@0 {
			compatible = "qcom,spmi-pmic";
			reg = <0 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8350-debug@1 {
			compatible = "qcom,spmi-pmic";
			reg = <1 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8350c-debug@2 {
			compatible = "qcom,spmi-pmic";
			reg = <2 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8350b-debug@3 {
			compatible = "qcom,spmi-pmic";
			reg = <3 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pmr735a-debug@4 {
			compatible = "qcom,spmi-pmic";
			reg = <4 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pmr735b-debug@5 {
			compatible = "qcom,spmi-pmic";
			reg = <5 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8450-debug@7 {
			compatible = "qcom,spmi-pmic";
			reg = <7 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8010-debug@8 {
			compatible = "qcom,spmi-pmic";
			reg = <8 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8010-debug@9 {
			compatible = "qcom,spmi-pmic";
			reg = <9 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};
	};

	qcom,pmic_glink {
		compatible = "qcom,pmic-glink";
		qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
		qcom,subsys-name = "lpass";
		qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
		depends-on-supply = <&ipcc_mproc>;

		battery_charger: qcom,battery_charger {
			compatible = "qcom,battery-charger";
		};

		ucsi: qcom,ucsi {
			compatible = "qcom,ucsi-glink";
		};

		altmode: qcom,altmode {
			compatible = "qcom,altmode-glink";
			#altmode-cells = <1>;
		};
	};

	qcom,pmic_glink_log {
		compatible = "qcom,pmic-glink";
		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";

		qcom,battery_debug {
			compatible = "qcom,battery-debug";
		};

		qcom,charger_ulog_glink {
			compatible = "qcom,charger-ulog-glink";
		};

		qcom,spmi_glink_debug {
			compatible = "qcom,spmi-glink-debug";
			#address-cells = <1>;
			#size-cells = <0>;
			depends-on-supply = <&spmi1_bus>;

			/* Primary SPMI bus */
			spmi@0 {
				reg = <0>;
				#address-cells = <2>;
				#size-cells = <0>;

				qcom,pm8350b-debug@3 {
					compatible = "qcom,spmi-pmic";
					reg = <3 SPMI_USID>;
					qcom,can-sleep;
				};
			};

			/* Secondary SPMI bus */
			spmi@1 {
				reg = <1>;
				#address-cells = <2>;
				#size-cells = <0>;
				smb1394_glink_debug: qcom,smb1394-debug@9 {
					compatible = "qcom,spmi-pmic";
					reg = <9 SPMI_USID>;
					qcom,can-sleep;
				};

				qcom,smb1394-debug@b {
					compatible = "qcom,spmi-pmic";
					reg = <11 SPMI_USID>;
					qcom,can-sleep;
				};

				qcom,smb1396-debug@d {
					compatible = "qcom,spmi-pmic";
					reg = <13 SPMI_USID>;
					qcom,can-sleep;
				};
			};
		};
	};

	qcom,secure-buffer {
		compatible = "qcom,secure-buffer";
		qcom,vmid-cp-camera-preview-ro;
	};

	soc-sleep-stats@c3f0000 {
		compatible = "qcom,rpmh-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ss-name = "modem", "adsp", "adsp_island",
			  "cdsp", "slpi", "slpi_island",
			  "apss";
		mboxes = <&qmp_aop 0>;
		ddr-freq-update;
	};

	subsystem-sleep-stats@c3f0000 {
		compatible = "qcom,subsystem-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ddr-freq-update;
	};

	sys-pm-vx@c320000 {
		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-cape";
		reg = <0xc320000 0x0400>;
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
	};

	rimps: qcom,rimps@17400000 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "qcom,rimps";
		reg =   <0x17400000 0x10>,
			<0x17d90000 0x2000>;
		#mbox-cells = <1>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	};

	scmi: qcom,scmi {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,scmi";
		mboxes = <&rimps 0>;
		mbox-names = "tx";
		shmem = <&cpu_scp_lpri>;

		scmi_plh: protocol@81 {
			reg = <0x81>;
			#clock-cells = <1>;
		};

		scmi_c1dcvs: protocol@87 {
			reg = <0x87>;
			#clock-cells = <1>;
		};
	};

	rimps_log: qcom,rimps_log@17d09c00 {
		compatible = "qcom,rimps-log";
		reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>;
		mboxes = <&rimps 1>;
	};

	ipcc_mproc: qcom,ipcc@ed18000 {
		compatible = "qcom,ipcc";
		reg = <0xed18000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	adsp_pas: remoteproc-adsp@03000000 {
		compatible = "qcom,cape-adsp-pas";
		reg = <0x03000000 0x10000>;
		status = "ok";

		cx-supply = <&VDD_LPI_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		mx-supply = <&VDD_LPI_MX_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		reg-names = "cx", "mx";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "crypto_ddr";

		memory-region = <&adsp_mem>;

		/* Inputs from ssc */
		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					<&adsp_smp2p_in 0 0>,
					<&adsp_smp2p_in 2 0>,
					<&adsp_smp2p_in 1 0>,
					<&adsp_smp2p_in 3 0>,
					<&adsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		glink_edge: glink-edge {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "adsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_LPASS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};

			qcom,pmic_glink_rpmsg {
				qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
			};

			qcom,pmic_glink_log_rpmsg {
				qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
				qcom,intents = <0x800 5
						0xc00 3
						0x2000 1>;
			};
		};
	};

	cdsp_pas: remoteproc-cdsp@32300000 {
		compatible = "qcom,cape-cdsp-pas";
		reg = <0x32300000 0x10000>;
		status = "ok";

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-supply = <&VDD_MXC_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		reg-names = "cx","mx";

		memory-region = <&cdsp_mem>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "rproc_ddr", "crypto_ddr";

		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					<&cdsp_smp2p_in 0 0>,
					<&cdsp_smp2p_in 2 0>,
					<&cdsp_smp2p_in 1 0>,
					<&cdsp_smp2p_in 3 0>,
					<&cdsp_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		glink-edge {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "cdsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_CDSP
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};
			qcom,msm_cdsprm_rpmsg {
				compatible = "qcom,msm-cdsprm-rpmsg";
				qcom,glink-channels = "cdsprmglink-apps-dsp";
				qcom,intents = <0x20 12>;

				msm_cdsp_rm: qcom,msm_cdsp_rm {
					compatible = "qcom,msm-cdsp-rm";
					qcom,qos-cores = <0 1 2 3>;
					qcom,qos-latency-us = <70>;
					qcom,qos-maxhold-ms = <20>;
				};
			};
		};
	};

	modem_pas: remoteproc-mss@04080000 {
		compatible = "qcom,cape-modem-pas";
		reg = <0x4080000 0x10000>;
		status = "ok";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mx-supply = <&VDD_MODEM_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		reg-names = "cx", "mx";


		qcom,qmp = <&aoss_qmp>;

		interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "rproc_ddr","crypto_ddr";

		memory-region = <&mpss_mem &system_cma>;

		/* Inputs from mss */
		interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>,
					<&modem_smp2p_in 0 0>,
					<&modem_smp2p_in 2 0>,
					<&modem_smp2p_in 1 0>,
					<&modem_smp2p_in 3 0>,
					<&modem_smp2p_in 7 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack",
				"shutdown-ack";

		/* Outputs to mss */
		qcom,smem-states = <&modem_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		glink-edge {
			qcom,remote-pid = <1>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "mpss_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_MPSS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "modem";
			qcom,glink-label = "mpss";

			qcom,modem_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,modem_ds {
				qcom,glink-channels = "DS";
				qcom,intents = <0x4000 0x2>;
			};
		};
	};

	/* PIL spss node - for loading Secure Processor */
	spss_pas: remoteproc-spss@1880000 {
		compatible = "qcom,cape-spss-pas";
		ranges;
		reg = <0x188101c 0x4>,
		      <0x1881024 0x4>,
		      <0x1881028 0x4>,
		      <0x188103c 0x4>,
		      <0x1881100 0x4>,
		      <0x1882014 0x4>;
		reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
			    "rmb_err", "rmb_general_purpose", "rmb_err_spare2";
		interrupts = <0 352 1>;

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		status = "disabled";

		memory-region = <&spss_region_mem>;
		qcom,spss-scsr-bits = <24 25>;
		qcom,extra-size = <4096>;

		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "crypto_ddr";

		glink-edge {
			qcom,remote-pid = <8>;
			mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "spss_spss";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_SPSS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			reg = <0x1885008 0x8>,
			      <0x1885010 0x4>;
			reg-names = "qcom,spss-addr",
				    "qcom,spss-size";

			label = "spss";
			qcom,glink-label = "spss";
		};
	};

	qcom,spcom {
		compatible = "qcom,spcom";

		qcom,rproc-handle = <&spss_pas>;
		qcom,boot-enabled;
		/* predefined channels, remote side is server */
		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
		/* sp2soc rmb shared register physical address and bmsk */
		qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
		qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
		qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
		/* soc2sp rmb shared register physical address */
		qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
		qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
		status = "disabled";
	};

	spss_utils: qcom,spss_utils {
		compatible = "qcom,spss-utils";
		/* spss fuses physical address */
		qcom,rproc-handle = <&spss_pas>;
		qcom,spss-fuse1-addr = <0x221C8214>;
		qcom,spss-fuse1-bit = <8>;
		qcom,spss-fuse2-addr = <0x221C8214>;
		qcom,spss-fuse2-bit = <7>;
		qcom,spss-dev-firmware-name  = "spss1d.mdt";  /* 8 chars max */
		qcom,spss-test-firmware-name = "spss1t.mdt";  /* 8 chars max */
		qcom,spss-prod-firmware-name = "spss1p.mdt";  /* 8 chars max */
		qcom,spss-debug-reg-addr = <0x01886020>;
		qcom,spss-debug-reg-addr1 = <0x01888020>;
		qcom,spss-debug-reg-addr3 = <0x0188C020>;
		qcom,spss-emul-type-reg-addr = <0x01fc8004>;
		pil-mem = <&spss_region_mem>;
		qcom,pil-size = <0x0F0000>; // padding to 960KB
		status = "disabled";
	};

	qcom,rmtfs_sharedmem@0 {
		compatible = "qcom,sharedmem-uio";
		reg = <0x0 0x280000>;
		reg-names = "rmtfs";
		qcom,client-id = <0x00000001>;
	};

	sdhc2_opp_table: sdhc2-opp-table {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-peak-kBps = <160000 100000>;
			opp-avg-kBps = <50000 0>;
		};

		opp-202000000 {
			opp-hz = /bits/ 64 <202000000>;
			opp-peak-kBps = <200000 120000>;
			opp-avg-kBps = <104000 0>;
		};
	};

	sdhc_2: sdhci@8804000 {
		status = "disabled";

		compatible = "qcom,sdhci-msm-v5";
		reg = <0x08804000 0x1000>;
		reg-names = "hc_mem";

		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		bus-width = <4>;
		no-sdio;
		no-mmc;
		qcom,uses_level_shifter;
		qcom,dll_lock_bist_fail_wa;

		clocks = <&clock_gcc GCC_SDCC2_AHB_CLK>,
			<&clock_gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x0007442C 0x0 0x08
					0x090106C0 0x80040868>;

		iommus = <&apps_smmu 0x4A0 0x0>;
		dma-coherent;
		qcom,iommu-dma = "fastmap";

		interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";
		operating-points-v2 = <&sdhc2_opp_table>;

		qos0 {
			mask = <0xf0>;
			vote = <44>;
		};

		qos1 {
			mask = <0x0f>;
			vote = <44>;
		};
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	qcom,qsee_ipc_irq_bridge {
		compatible = "qcom,qsee-ipc-irq-bridge";

		qcom,qsee-ipc-irq-spss {
			qcom,dev-name = "qsee_ipc_irq_spss";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_SPSS
				      IPCC_MPROC_SIGNAL_TZ
				      IRQ_TYPE_EDGE_RISING>;
			label = "spss";
		};
	};

	ufsphy_mem: ufsphy_mem@1d80000 {
		reg = <0x1d80000 0x2000>;
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;
		clock-names = "ref_clk_src",
			"ref_aux_clk", "qref_clk",
			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_PHY_PHY_AUX_CLK>,
			<&clock_gcc GCC_UFS_0_CLKREF_EN>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
			<&clock_gcc UFS_PHY_RX_SYMBOL_0_CLK>,
			<&clock_gcc UFS_PHY_RX_SYMBOL_1_CLK>,
			<&clock_gcc UFS_PHY_TX_SYMBOL_0_CLK>;
		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>,
		      <0x1d88000 0x8000>,
		      <0x1d90000 0x9000>;
		reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;

		qcom,prime-mask = <0x70>;
		qcom,silver-mask = <0x0f>;
		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&clock_gcc GCC_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_UFS_PHY_AHB_CLK>,
			<&clock_gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&clock_gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&clock_gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<75000000 850000000>,
			<0 0>,
			<0 0>,
			<75000000 850000000>,
			<75000000 850000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		qcom,ufs-bus-bw,name = "ufshc_mem";
		qcom,ufs-bus-bw,num-cases = <26>;
		qcom,ufs-bus-bw,num-paths = <2>;
		qcom,ufs-bus-bw,vectors-KBps =

		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<0 0>, <0 0>,          /* No vote */
		<922 0>, <1000 0>,     /* PWM G1 */
		<1844 0>, <1000 0>,    /* PWM G2 */
		<3688 0>, <1000 0>,    /* PWM G3 */
		<7376 0>, <1000 0>,    /* PWM G4 */
		<1844 0>, <1000 0>,    /* PWM G1 L2 */
		<3688 0>, <1000 0>,    /* PWM G2 L2 */
		<7376 0>, <1000 0>,    /* PWM G3 L2 */
		<14752 0>, <1000 0>,   /* PWM G4 L2 */
		<127796 0>, <1000 0>,  /* HS G1 RA */
		<255591 0>, <1000 0>,  /* HS G2 RA */
		<1492582 0>, <102400 0>,  /* HS G3 RA */
		<2915200 0>, <204800 0>,  /* HS G4 RA */
		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
		<149422 0>, <1000 0>,  /* HS G1 RB */
		<298189 0>, <1000 0>,  /* HS G2 RB */
		<1492582 0>, <102400 0>,  /* HS G3 RB */
		<2915200 0>, <204800 0>,  /* HS G4 RB */
		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
		<596378 0>, <1000 0>,  /* HS G2 RB L2 */

		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
		<7643136 12000000>, <409600 409600>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
		"MAX";

		reset-gpios = <&tlmm 210 GPIO_ACTIVE_LOW>;
		resets = <&clock_gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		iommus = <&apps_smmu 0xE0 0x0>;
		qcom,iommu-dma = "fastmap";
		dma-coherent;

		/* Multilevel clock scaling support for higher ufs clock freq */
		multi-level-clk-scaling-support;
		axi-turbo-clk-freq = <850000000>;
		axi-turbo-l1-clk-freq = <850000000>;
		ice-turbo-clk-freq = <850000000>;
		ice-turbo-l1-clk-freq = <850000000>;
		unipro-turbo-clk-freq = <850000000>;
		unipro-turbo-l1-clk-freq = <850000000>;

		/* CGC bit needs to disable fot target supporting higher ufs clock freq */
		disable-cgc;

		status = "disabled";
		qos0 {
			mask = <0xf0>;
			vote = <44>;
			perf;
		};

		qos1 {
			mask = <0x0f>;
			vote = <44>;
		};
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,waipio-clk_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,waipio-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	config_noc: interconnect@1500000 {
		reg = <0x1500000 0x1C000>;
		compatible = "qcom,waipio-config_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	system_noc: interconnect@1680000 {
		reg = <0x1680000 0x1E200>;
		compatible = "qcom,waipio-system_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	pcie_noc: interconnect@16c0000 {
		reg = <0x16C0000 0xE280>;
		compatible = "qcom,waipio-pcie_anoc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	aggre1_noc: interconnect@16e0000 {
		reg = <0x16e0000 0x1C080>;
		compatible = "qcom,waipio-aggre1_noc";
		#interconnect-cells = <1>;
		clocks =
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	aggre2_noc: interconnect@1700000 {
		reg = <0x1700000 0x31080>;
		compatible = "qcom,waipio-aggre2_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		clocks =
			<&clock_gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&clock_rpmh RPMH_IPA_CLK>;
	};

	mmss_noc: interconnect@1740000 {
		reg = <0x1740000 0x1f080>;
		compatible = "qcom,waipio-mmss_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	gem_noc: interconnect@19100000 {
		reg = <0x19100000 0xBB800>;
		compatible = "qcom,waipio-gem_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp_bcm_voter>;
	};

	nsp_noc: interconnect@320C0000 {
		reg = <0x320C0000 0x10000>;
		compatible = "qcom,waipio-nsp_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	lpass_ag_noc: interconnect@3c40000 {
		reg = <0x3c40000 0x17200>;
		compatible = "qcom,waipio-lpass_ag_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	eud: qcom,msm-eud@88e0000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupt-parent = <&pdc>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x088e0000 0x2000>,
			<0x088e2000 0x1000>;
		reg-names = "eud_base", "eud_mode_mgr2";

		clocks = <&clock_gcc GCC_EUSB3_0_CLKREF_EN>;
		clock-names = "eud_clkref_clk";

		qcom,secure-eud-en;
		status = "ok";
	};

	microdump_modem {
		compatible = "qcom,microdump_modem";
	};

	mini_dump_node {
		compatible = "qcom,minidump";
	};

	va_mini_dump {
		compatible = "qcom,va-minidump";
		memory-region = <&va_md_mem>;
		status = "ok";
	};

	vendor_hooks: qcom,cpu-vendor-hooks {
		compatible = "qcom,cpu-vendor-hooks";
	};

	logbuf: qcom,logbuf-vendor-hooks {
		compatible = "qcom,logbuf-vendor-hooks";
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	qcom,msm-imem@146aa000 {
		compatible = "qcom,msm-imem";
		reg = <0x146aa000 0x1000>;
		ranges = <0x0 0x146aa000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10 {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};

		pil@94c {
			compatible = "qcom,pil-reloc-info";
			reg = <0x94c 0xc8>;
		};

		pil@6dc {
			compatible = "qcom,msm-imem-pil-disable-timeout";
			reg = <0x6dc 0x4>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};
	};

	qcom,chd {
		compatible = "qcom,core-hang-detect";
		label = "core";
		qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058
			0x17840058 0x17850058 0x17860058 0x17870058>;
		qcom,config-arr = <0x17800060 0x17810060 0x17820060 0x17830060
			0x17840060 0x17850060 0x17860060 0x17870060>;
	};

	dload_mode {
		compatible = "qcom,dload-mode";
	};

	microdump_modem {
		compatible = "qcom,microdump_modem";
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-dsps {
		compatible = "qcom,smp2p";
		qcom,smem = <481>, <430>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <3>;

		dsps_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		dsps_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-modem {
		compatible = "qcom,smp2p";
		qcom,smem = <435>, <428>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_MPSS IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <1>;

		modem_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		modem_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_ipa_1_out: qcom,smp2p-ipa-1-out {
			qcom,entry-name = "ipa";
			#qcom,smem-state-cells = <1>;
		};

		/* ipa - inbound entry from mss */
		smp2p_ipa_1_in: qcom,smp2p-ipa-1-in {
			qcom,entry-name = "ipa";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-at-mdm0 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DS";
			qcom,glinkpkt-dev-name = "at_mdm0";
		};

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};

		qcom,glinkpkt-data40-cntl {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA40_CNTL";
			qcom,glinkpkt-dev-name = "smdcntl8";
		};

		qcom,glinkpkt-data1 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA1";
			qcom,glinkpkt-dev-name = "smd7";
		};

		qcom,glinkpkt-data4 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA4";
			qcom,glinkpkt-dev-name = "smd8";
		};

		qcom,glinkpkt-data11 {
			qcom,glinkpkt-edge = "mpss";
			qcom,glinkpkt-ch-name = "DATA11";
			qcom,glinkpkt-dev-name = "smd11";
		};
	};

	qcom,glink {
		compatible = "qcom,glink";
	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,waipio-aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
			      IPCC_MPROC_SIGNAL_GLINK_QMP
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
			  IPCC_MPROC_SIGNAL_GLINK_QMP>;

		#power-domain-cells = <1>;
		#clock-cells = <0>;
	};

	qmp_aop: qcom,qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qmp_tme: qcom,qmp-tme {
		compatible = "qcom,qmp-mbox";
		qcom,remote-pid = <14>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
			  IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "tme_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_TME
			      IPCC_MPROC_SIGNAL_GLINK_QMP
			      IRQ_TYPE_EDGE_RISING>;

		label = "tme";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	qcom,tmecom-qmp-client {
		compatible = "qcom,tmecom-qmp-client";
		mboxes = <&qmp_tme 0>;
		mbox-names = "tmecom";
		label = "tmecom";
		depends-on-supply = <&qmp_tme>;
	};

	slpi_pas: remoteproc-slpi@02400000 {
		compatible = "qcom,waipio-slpi-pas";
		reg = <0x02400000 0x10000>;
		status = "ok";

		cx-supply = <&VDD_LPI_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		mx-supply = <&VDD_LPI_MX_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		reg-names = "cx", "mx";

		clocks = <&clock_rpmh RPMH_CXO_CLK>;
		clock-names = "xo";

		qcom,qmp = <&aoss_qmp>;

		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "crypto_ddr";

		memory-region = <&slpi_mem>;

		/* Inputs from ssc */
		interrupts-extended = <&pdc 9 IRQ_TYPE_EDGE_RISING>,
					<&dsps_smp2p_in 0 0>,
					<&dsps_smp2p_in 2 0>,
					<&dsps_smp2p_in 1 0>,
					<&dsps_smp2p_in 3 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&dsps_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		glink-edge {
			qcom,remote-pid = <3>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_SLPI
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "dsps_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_SLPI
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			label = "slpi";
			qcom,glink-label = "dsps";

			qcom,slpi_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,net-id = <2>;
				qcom,low-latency;
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;

				qcom,no-wake-svc = <0x190>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};
		};
	};

	ssc_sensors: qcom,msm-ssc-sensors {
		compatible = "qcom,msm-ssc-sensors";
		status = "ok";
		qcom,firmware-name = "slpi";
		qcom,rproc-handle = <&slpi_pas>;
	};

	qcom,msm_gsi {
		compatible = "qcom,msm_gsi";
	};

	qcom,rmnet-ipa {
		compatible = "qcom,rmnet-ipa3";
		qcom,rmnet-ipa-ssr;
		qcom,ipa-platform-type-msm;
		qcom,ipa-advertise-sg-support;
		qcom,ipa-napi-enable;
	};

	qcom,ipa_fws {
		compatible = "qcom,pil-tz-generic";
		qcom,pas-id = <0xf>;
		qcom,firmware-name = "ipa_fws";
		qcom,pil-force-shutdown;
		status = "disabled";
	};

	ipa_hw: qcom,ipa@3e00000 {
		compatible = "qcom,ipa";
		reg =
			<0x3e00000 0x84000>,
			<0x3e04000 0xfc000>;
		reg-names = "ipa-base", "gsi-base";
		pas-ids = <0xf>;
		firmware-names = "ipa_fws";
		memory-regions = <&ipa_gsi_mem>;
		qcom,ipa-cfg-offset = <0x0140000>;
		interrupts =
			<0 654 IRQ_TYPE_LEVEL_HIGH>,
			<0 432 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "ipa-irq", "gsi-irq";
		qcom,ipa-hw-ver = <22>; /* IPA core version = IPAv5.1 */
		qcom,ipa-hw-mode = <0>;
		qcom,platform-type = <1>; /* MSM platform */
		qcom,ee = <0>;
		qcom,entire-ipa-block-size = <0x200000>;
		qcom,use-ipa-tethering-bridge;
		qcom,modem-cfg-emb-pipe-flt;
		qcom,ipa-wdi3-over-gsi;
		qcom,arm-smmu;
		qcom,smmu-fast-map;
		qcom,use-64-bit-dma-mask;
		qcom,ipa-endp-delay-wa-v2;
		qcom,ipa-ulso-wa;
		qcom,lan-rx-napi;
		qcom,tx-napi;
		qcom,tx-poll;
		qcom,wan-use-skb-page;
		qcom,rmnet-ctl-enable;
		qcom,rmnet-ll-enable;
		qcom,ipa-uc-holb-monitor;
		qcom,ipa-holb-monitor-poll-period = <5>;
		qcom,ipa-holb-monitor-max-cnt-wlan = <10>;
		qcom,ipa-holb-monitor-max-cnt-usb = <10>;
		qcom,ipa-holb-monitor-max-cnt-11ad = <10>;
		qcom,register-collection-on-crash;
		qcom,testbus-collection-on-crash;
		qcom,non-tn-collection-on-crash;
		qcom,tx-wrapper-cache-max-size = <400>;
		qcom,ipa-gpi-event-rp-ddr;
		qcom,ulso-supported;
		qcom,ulso-ip-id-min-linux-val = <0>;
		qcom,ulso-ip-id-max-linux-val = <0xffff>;
		qcom,ulso-ip-id-min-windows-val = <0>;
		qcom,ulso-ip-id-max-windows-val = <0x7fff>;
		qcom,max_num_smmu_cb = <4>;
		clock-names = "core_clk";
		clocks = <&clock_rpmh RPMH_IPA_CLK>;
		qcom,interconnect,num-cases = <5>;
		qcom,interconnect,num-paths = <3>;
		interconnects = <&aggre2_noc MASTER_IPA &gem_noc SLAVE_LLCC>,
			<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_IPA_CFG>;
		interconnect-names = "ipa_to_llcc", "llcc_to_ebi1", "appss_to_ipa";
		/* No vote */
		qcom,no-vote =
		<0 0 0 0 0 0>;

		/* SVS2 */
		qcom,svs2 =
		<590000 0 590000 1900000 0 76800>;

		/* SVS */
		qcom,svs =
		<1200000 0 1200000 2800000 0 150000>;

		/* NOMINAL */
		qcom,nominal =
		<2400000 0 2400000 5500000 0 400000>;

		/* TURBO */
		qcom,turbo =
		<3600000 0 3600000 5500000 0 400000>;

		qcom,bus-vector-names = "MIN", "SVS2", "SVS", "NOMINAL",
			"TURBO";
		qcom,throughput-threshold = <2000 4000 8000>;
		qcom,scaling-exceptions = <>;

		/* smp2p information */
		qcom,smp2p_map_ipa_1_out {
			compatible = "qcom,smp2p-map-ipa-1-out";
			qcom,smem-states = <&smp2p_ipa_1_out 0>;
			qcom,smem-state-names = "ipa-smp2p-out";
		};

		qcom,smp2p_map_ipa_1_in {
			compatible = "qcom,smp2p-map-ipa-1-in";
			interrupts-extended = <&smp2p_ipa_1_in 0 0>;
			interrupt-names = "ipa-smp2p-in";
		};

		ipa_smmu_ap: ipa_smmu_ap {
			compatible = "qcom,ipa-smmu-ap-cb";
			iommus = <&apps_smmu 0x5c0 0x0>;
			qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
			qcom,additional-mapping =
				/* modem tables in IMEM */
				<0x146A8000 0x146A8000 0x2000>;
			qcom,iommu-dma = "atomic";
			dma-coherent;
			qcom,ipa-q6-smem-size = <36864>;
		};

		ipa_smmu_wlan: ipa_smmu_wlan {
			compatible = "qcom,ipa-smmu-wlan-cb";
			iommus = <&apps_smmu 0x5c1 0x0>;
			qcom,iommu-dma = "atomic";
		};

		ipa_smmu_uc: ipa_smmu_uc {
			compatible = "qcom,ipa-smmu-uc-cb";
			iommus = <&apps_smmu 0x5c2 0x0>;
			qcom,iommu-dma-addr-pool = <0x20000000 0x20000000>;
			qcom,iommu-dma = "atomic";
		};

		ipa_smmu_11ad: ipa_smmu_11ad {
			compatible = "qcom,ipa-smmu-11ad-cb";
			iommus = <&apps_smmu 0x5c3 0x0>;
			dma-coherent;
			qcom,shared-cb;
			qcom,iommu-group = <>;
		};
	};

	qcom,gh_vm_loader_sec@e0b00000 {
		compatible = "qcom,gh-vm-loader-sec";
		qcom,pas-id = <28>;
		qcom,vmid = <45>;
		qcom,firmware-name = "trustedvm";
		memory-region = <&trust_ui_vm_mem>;
	};

	qcom,gh_vm_loader_sec@e0600000 {
		compatible = "qcom,gh-vm-loader-sec";
		qcom,pas-id = <35>;
		qcom,vmid = <50>;
		qcom,firmware-name = "cpusys_vm";
		qcom,no-shutdown;
		memory-region = <&cpusys_vm_mem>;
	};

	tlmm-vm-mem-access {
		compatible = "qcom,tlmm-vm-mem-access";
		qcom,master;
		tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388 317 318 319 320 321 322>;
	};

	qcom,guestvm_loader@e0b00000 {
		compatible = "qcom,guestvm-loader";
		qcom,pas-id = <28>;
		qcom,isolate-cpus;
		qcom,vmid = <45>;
		qcom,firmware-name = "trustedvm";
		qcom,reserved-cpus = <0x5>, <0x6>;
		qcom,unisolate-timeout-ms = <12000>;
		memory-region = <&trust_ui_vm_mem>;
	};

	qcom,guestvm_loader@e0600000 {
		compatible = "qcom,guestvm-loader";
		qcom,pas-id = <35>;
		qcom,vmid = <50>;
		qcom,firmware-name = "cpusys_vm";
		memory-region = <&cpusys_vm_mem>;
	};

	cache-controller@19200000 {
		compatible = "qcom,cape-llcc", "qcom,llcc-v21";
		reg = <0x19200000 0x580000> , <0x19a00000 0x80000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;

		llcc-perfmon {
			compatible = "qcom,llcc-perfmon";
			clocks = <&aoss_qmp QDSS_CLK>;
			clock-names = "qdss_clk";
		};
	};

	qcom,memshare {
		compatible = "qcom,memshare";

		qcom,client_1 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x0>;
			qcom,client-id = <0>;
			qcom,allocate-boot-time;
			label = "modem";
		};

		qcom,client_2 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x0>;
			qcom,client-id = <2>;
			label = "modem";
		};

		qcom,client_3 {
			compatible = "qcom,memshare-peripheral";
			qcom,peripheral-size = <0x500000>;
			qcom,client-id = <1>;
			qcom,allocate-on-request;
			label = "modem";
		};
	};

	mhi_qrtr_cnss {
		compatible = "qcom,qrtr-mhi";
		qcom,dev-id = <0x1103>;
		qcom,net-id = <0>;
		qcom,low-latency;
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
		qcom,rproc-handle = <&cdsp_pas>;
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem_heap>;
		restrict-access;
	};

	msm_fastrpc: qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,adsp-remoteheap-vmid = <22 37>;
		qcom,fastrpc-adsp-audio-pdr;
		qcom,fastrpc-slpi-sensors-pdr;
		qcom,rpc-latency-us = <235>;
		qcom,fastrpc-gids = <2908>;
		qcom,qos-cores = <0 1 2 3>;

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2161 0x0400>,
					 <&apps_smmu 0x1021 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2162 0x0400>,
					 <&apps_smmu 0x1022 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2163 0x0400>,
					 <&apps_smmu 0x1023 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2164 0x0400>,
					 <&apps_smmu 0x1024 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2165 0x0400>,
					 <&apps_smmu 0x1025 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2166 0x0400>,
					 <&apps_smmu 0x1026 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2167 0x0400>,
					 <&apps_smmu 0x1027 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x2168 0x0400>,
					 <&apps_smmu 0x1028 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x2169 0x0400>,
					 <&apps_smmu 0x1029 0x0420>;
			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1803 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1804 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x1805 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x0541 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb14 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x0542 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb15 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "sdsprpc-smd";
			iommus = <&apps_smmu 0x0543 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			shared-cb = <4>;
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb16 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x102B 0x0420>,
					 <&apps_smmu 0x216B 0x0400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb17 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x102C 0x0420>,
					 <&apps_smmu 0x216C 0x0400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb18 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x102D 0x0420>,
					 <&apps_smmu 0x216D 0x0400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb19 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x102E 0x0420>,
					 <&apps_smmu 0x216E 0x0400>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};
	};

	wlan: qcom,cnss-qca6490@b0000000 {
		compatible = "qcom,cnss-qca6490";
		reg = <0xb0000000 0x10000>;
		reg-names = "smmu_iova_ipa";
		wlan-en-gpio = <&tlmm 80 0>;
		qcom,bt-en-gpio = <&tlmm 81 0>;
		qcom,sw-ctrl-gpio = <&tlmm 82 0>;
		pinctrl-names = "wlan_en_active", "wlan_en_sleep";
		pinctrl-0 = <&cnss_wlan_en_active>;
		pinctrl-1 = <&cnss_wlan_en_sleep>;
		qcom,wlan;
		qcom,wlan-rc-num = <0>;
		qcom,wlan-ramdump-dynamic = <0x420000>;
		qcom,wlan-cbc-enabled;
		use-pm-domain;
		cnss-enable-self-recovery;
		qcom,same-dt-multi-dev;
		mboxes = <&qmp_aop 0>;
		qcom,vreg_ipa="s3e";
		qcom,xo-clk-gpio = <&tlmm 204 0>;

		vdd-wlan-aon-supply = <&S2E>;
		qcom,vdd-wlan-aon-config = <1012000 1040000 0 0 1>;
		vdd-wlan-dig-supply = <&S11B>;
		qcom,vdd-wlan-dig-config = <966000 1170000 0 0 1>;
		vdd-wlan-io-supply = <&S10B>;
		qcom,vdd-wlan-io-config = <1800000 1800000 0 0 1>;
		vdd-wlan-rfa1-supply = <&S1C>;
		qcom,vdd-wlan-rfa1-config = <1900000 2024000 0 0 1>;
		vdd-wlan-rfa2-supply = <&S12B>;
		qcom,vdd-wlan-rfa2-config = <1350000 2040000 0 0 1>;
		wlan-ant-switch-supply = <&L7E>;
		qcom,wlan-ant-switch-config = <2800000 2800000 0 0 1>;

		interconnects =
		<&pcie_noc MASTER_PCIE_0 &pcie_noc SLAVE_ANOC_PCIE_GEM_NOC>,
		<&gem_noc MASTER_ANOC_PCIE_GEM_NOC &mc_virt SLAVE_EBI1>;
		interconnect-names = "pcie_to_memnoc", "memnoc_to_ddr";


		qcom,icc-path-count = <2>;
		qcom,bus-bw-cfg-count = <9>;
		qcom,bus-bw-cfg =
		/** ICC Path 1 **/
		<0 0>, /* no vote */
		/* idle: 0-18 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
		<2250 1600000>,
		/* low: 18-60 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
		<7500 1600000>,
		/* medium: 60-240 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
		<30000 1600000>,
		/* high: 240-1200 Mbps snoc/anoc: 100 Mhz ddr: 451.2 MHz */
		<100000 1600000>,
		/* very high: > 1200 Mbps snoc/anoc: 403 Mhz ddr: 1555 MHz */
		<175000 6448000>,
		/* ultra high: DBS mode snoc/anoc: 403 Mhz ddr: 2092 MHz */
		<175000 6448000>,
		/* super high: DBS mode snoc/anoc: 533 Mhz ddr: 3.2GHz */
		<175000 8528000>,
		/* low (latency critical): 18-60 Mbps snoc/anoc: 200 Mhz
		 * ddr: 547.2 MHz
		 */
		<7500 3200000>,

		/** ICC Path 2 **/
		<0 0>,
		/* ddr: 451.2 MHz */
		<2250 1804800>,
		/* ddr: 451.2 MHz */
		<7500 1804800>,
		/* ddr: 451.2 MHz */
		<30000 1804800>,
		/* ddr: 451.2 MHz */
		<100000 1804800>,
		/* ddr: 1555 MHz */
		<175000 6220800>,
		/* ddr: 2092 MHz */
		<175000 8368000>,
		/* ddr: 3.2 GHz */
		<175000 12800000>,
		/* ddr: 547.2 MHz */
		<7500 2188800>;
	};

	hyp_core_ctl: qcom,hyp-core-ctl {
		compatible = "qcom,hyp-core-ctl";
		status = "ok";
	};

};

&clock_gcc {
	compatible = "qcom,cape-gcc", "syscon";
};

&clock_videocc {
	compatible = "qcom,cape-videocc", "syscon";
};

&clock_camcc {
	compatible = "qcom,cape-camcc", "syscon";
};

&clock_dispcc {
	compatible = "qcom,cape-dispcc", "syscon";
};

&clock_gpucc {
	compatible = "qcom,cape-gpucc", "syscon";
};

#include "cape-pinctrl.dtsi"
#include "waipio-qupv3.dtsi"
#include "cape-regulators.dtsi"
#include "cape-coresight.dtsi"
#include "cape-debug.dtsi"
#include "msm-arm-smmu-waipio.dtsi"
#include "cape-dma-heaps.dtsi"
#include "cape-gpu.dtsi"
#include "cape-thermal.dtsi"
#include "cape-usb.dtsi"
#include "cape-pcie.dtsi"
#include "msm-rdbg.dtsi"
#include "ipcc-test.dtsi"

&qupv3_se7_2uart {
	status = "ok";
};

&qupv3_se20_4uart {
	status = "ok";
};

&qupv3_se5_i2c {
	status = "ok";
	fsa4480: fsa4480@42 {
		compatible = "qcom,fsa4480-i2c";
		reg = <0x42>;
	};
};

&pcie0_rp {
	#address-cells = <5>;
	#size-cells = <0>;

	cnss_pci: cnss_pci {
		reg = <0 0 0 0 0>;
		qcom,iommu-group = <&cnss_pci_iommu_group>;
		memory-region = <&cnss_wlan_mem>;

		#address-cells = <1>;
		#size-cells = <1>;

		cnss_pci_iommu_group: cnss_pci_iommu_group {
			qcom,iommu-msi-size = <0x1000>;
			qcom,iommu-dma-addr-pool = <0xa0000000 0x10000000>;
			qcom,iommu-dma = "fastmap";
			qcom,iommu-pagetable = "coherent";
			qcom,iommu-faults = "stall-disable", "HUPCF", "no-CFRE",
					    "non-fatal";
		};
	};
};
