


&soc {
	tlmm: pinctrl@f100000 {
		compatible = "qcom,sdxlemur-pinctrl";
		reg = <0xf100000 0x300000>;
		reg-names = "pinctrl";
		interrupts = <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		interrupt-parent = <&intc>;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;

		uart3_console_active: uart3_console_active {
			mux {
				pins = "gpio8", "gpio9";
				function = "blsp_uart3";
			};

			config {
				pins = "gpio8", "gpio9";
				drive-strength = <2>;
				bias-disable;
				};
			};

		uart3_console_sleep: uart3_console_sleep {
			mux {
				pins = "gpio8", "gpio9";
				function = "blsp_uart3";
			};

			config {
				pins = "gpio8", "gpio9";
				drive-strength = <2>;
				bias-disable;
			};
		};

		pcie0 {
			pcie0_clkreq_default: pcie0_clkreq_default {
				mux {
					pins = "gpio56";
					function = "pcie_clkreq";
				};

				config {
					pins = "gpio56";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			pcie0_perst_default: pcie0_perst_default {
				mux {
					pins = "gpio57";
					function = "gpio";
				};

				config {
					pins = "gpio57";
					drive-strength = <2>;
					bias-pull-down;
				};
			};

			pcie0_wake_default: pcie0_wake_default {
				mux {
					pins = "gpio53";
					function = "gpio";
				};

				config {
					pins = "gpio53";
					drive-strength = <2>;
					bias-pull-up;
				};
			};

			pcie0_clkreq_sleep: pcie0_clkreq_sleep {
				mux {
					pins = "gpio56";
					function = "gpio";
				};

				config {
					pins = "gpio56";
					drive-strength = <2>;
					bias-pull-up;
				};
			};
		};
	};
};
