%YAML 1.2
---
$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,cape-pinctrl.yaml#
$schema: http://devicetree.org/meta-schemas/core.yaml#

title: Qualcomm Technologies, Inc. CAPE TLMM block

description: |
  This binding describes the Top Level Mode Multiplexer block found in the
  CAPE platform.

properties:
  compatible:
      Usage: required
      Value type: <string>
      Definition: must be "qcom,cape-pinctrl"

  reg:
      Usage: required
      Value type: <prop-encoded-array>
      Definition: the base address and size of the TLMM register space.

  interrupts:
      Usage: required
      Value type: <prop-encoded-array>
      Definition: should specify the TLMM summary IRQ.

  interrupt-controller:
      Usage: required
      Value type: <none>
      Definition: identifies this node as an interrupt controller

  #interrupt-cells:
      Usage: required
      Value type: <u32>
      Definition: must be 2. Specifying the pin number and flags, as defined
                  in <dt-bindings/interrupt-controller/irq.h>

  gpio-controller:
      Usage: required
      Value type: <none>
      Definition: identifies this node as a gpio controller

  #gpio-cells:
      Usage: required
      Value type: <u32>
      Definition: must be 2. Specifying the pin number and flags, as defined
                  in <dt-bindings/gpio/gpio.h>

  wakeup-parent:
      Usage: optional
      Value type: <phandle>
      Definition: A phandle to the wakeup interrupt controller for the SoC.

  Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for
  a general description of GPIO and interrupt bindings.

  Please refer to pinctrl-bindings.txt in this directory for details of the
  common pinctrl bindings used by client devices, including the meaning of the
  phrase "pin configuration node".

  The pin configuration nodes act as a container for an arbitrary number of
  subnodes. Each of these subnodes represents some desired configuration for a
  pin, a group, or a list of pins or groups. This configuration can include the
  mux function to select on those pin(s)/group(s), and various pin configuration
  parameters, such as pull-up, drive strength, etc.


  PIN CONFIGURATION NODES:

  The name of each subnode is not important; all subnodes should be enumerated
  and processed purely based on their content.

  Each subnode only affects those parameters that are explicitly listed. In
  other words, a subnode that lists a mux function but no pin configuration
  parameters implies no information about any pin configuration parameters.
  Similarly, a pin subnode that describes a pullup parameter implies no
  information about e.g. the mux function.


  The following generic properties as defined in pinctrl-bindings.txt are valid
  to specify in a pin configuration subnode:

  pins:
        Usage: required
        Value type: <string-array>
        Definition: List of gpio pins affected by the properties specified in
                    this subnode.

        Valid pins:
                  gpio0-gpio169
                  Supports mux, bias and drive-strength

                  sdc2_clk, sdc2_cmd, sdc2_data, ufs_reset
                  Supports bias and drive-strength

  function:
        Usage: required
        Value type: <string>
        Definition: Specify the alternative function to be configured for the
                    specified pins. Functions are only valid for gpio pins.
        Valid values:
		gpio, atest_char, atest_char0, atest_char1, atest_char2,
		atest_char3, atest_usb0, atest_usb00, atest_usb01, atest_usb02,
		atest_usb03, audio_ref, cam_mclk, cci_async, cci_i2c,
		cci_timer0, cci_timer1, cci_timer2, cci_timer3, cci_timer4,
		cmu_rng0, cmu_rng1, cmu_rng2, cmu_rng3, coex_uart1, cri_trng,
		cri_trng0, cri_trng1, dbg_out, ddr_bist, ddr_pxi0, ddr_pxi1,
		dp0_hot, gcc_gp1, gcc_gp2, gcc_gp3, host2wlan_sol, ibi_i3c,
		jitter_bist, mdp_vsync, mdp_vsync0, mdp_vsync1, mdp_vsync2,
		mdp_vsync3, mi2s0_data0, mi2s0_data1, mi2s0_sck, mi2s0_ws,
		mi2s2_data0, mi2s2_data1, mi2s2_sck, mi2s2_ws, mi2s_mclk0,
		mi2s_mclk1, nav_gpio0, nav_gpio1, nav_gpio2, pcie0_clk,
		phase_flag0, phase_flag1, phase_flag10, phase_flag11,
		phase_flag12, phase_flag13, phase_flag14, phase_flag15,
		phase_flag16, phase_flag17, phase_flag18, phase_flag19,
		phase_flag2, phase_flag20, phase_flag21, phase_flag22,
		phase_flag23, phase_flag24, phase_flag25, phase_flag26,
		phase_flag27, phase_flag28, phase_flag29, phase_flag3,
		phase_flag30, phase_flag31, phase_flag4, phase_flag5,
		phase_flag6, phase_flag7, phase_flag8, phase_flag9,
		pll_bist, pll_clk, prng_rosc0, prng_rosc1, prng_rosc2,
		prng_rosc3, qdss_cti, qdss_gpio, qdss_gpio0, qdss_gpio1,
		qdss_gpio10, qdss_gpio11, qdss_gpio12, qdss_gpio13, qdss_gpio14,
		qdss_gpio15, qdss_gpio2, qdss_gpio3, qdss_gpio4, qdss_gpio5,
		qdss_gpio6, qdss_gpio7, qdss_gpio8, qdss_gpio9, qlink0_enable,
		qlink0_request, qlink0_wmss, qlink1_enable, qlink1_request,
		qlink1_wmss, qlink2_enable, qlink2_request, qlink2_wmss,
		qup0_se0, qup0_se1, qup0_se2, qup0_se3, qup0_se4, qup0_se5,
		qup0_se6, qup0_se7, qup1_se0, qup1_se1, qup1_se2, qup1_se3,
		qup1_se4, qup1_se5, qup1_se6, sd_write, tb_trig, tgu_ch0,
		tgu_ch1, tgu_ch2, tgu_ch3, tmess_prng0, tmess_prng1,
		tmess_prng2, tmess_prng3, tsense_pwm1, tsense_pwm2, uim0_clk,
		uim0_data, uim0_present, uim0_reset, uim1_clk, uim1_data,
		uim1_present, uim1_reset, usb0_hs, usb0_phy, vfr_0, vfr_1,
		vsense_trigger

  bias-disable:
    Usage: optional
    Value type: <none>
    Definition: The specified pins should be configured as no pull.

  bias-pull-down:
    Usage: optional
    Value type: <none>
    Definition: The specified pins should be configured as pull down.

  bias-pull-up:
    Usage: optional
    Value type: <none>
    Definition: The specified pins should be configured as pull up.

  output-high:
    Usage: optional
    Value type: <none>
    Definition: The specified pins are configured in output mode, driven high.
                  Not valid for sdc pins.

  output-low:
    Usage: optional
    Value type: <none>
    Definition: The specified pins are configured in output mode, driven low.
                  Not valid for sdc pins.

  drive-strength:
    Usage: optional
    Value type: <u32>
    Definition: Selects the drive strength for the specified pins, in mA.
    Valid values: 2, 4, 6, 8, 10, 12, 14 and 16

examples:
  - |
    tlmm: pinctrl@f000000 {
      compatible = "qcom,cape-pinctrl";
      reg = <0x0F000000 0x1000000>;
      interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
      gpio-controller;
      #gpio-cells = <2>;
      interrupt-controller;
      #interrupt-cells = <2>;
    };

