#include <bindings/qcom,audio-ext-clk.h>
#include <bindings/qcom,lpass-cdc-clk-rsc.h>
#include <bindings/audio-codec-port-types.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include "waipio-lpi.dtsi"

&lpass_cdc {
	qcom,num-macros = <4>;
	qcom,lpass-cdc-version = <6>;
	#address-cells = <1>;
	#size-cells = <1>;
	lpass-cdc-clk-rsc-mngr {
		compatible = "qcom,lpass-cdc-clk-rsc-mngr";
		qcom,fs-gen-sequence = <0x3000 0x1 0x1>, <0x3004 0x3 0x3>,
					<0x3004 0x3 0x1>, <0x3080 0x2 0x2>;
	qcom,rx_mclk_mode_muxsel = <0x033A40D8>;
	qcom,wsa_mclk_mode_muxsel = <0x033A20E0>;
	qcom,va_mclk_mode_muxsel = <0x03420000>;
	clock-names = "tx_core_clk", "rx_core_clk", "wsa_core_clk",
		"va_core_clk", "wsa2_core_clk", "rx_tx_core_clk",
		"wsa_tx_core_clk", "wsa2_tx_core_clk";
	clocks = <&clock_audio_tx_1 0>, <&clock_audio_rx_1 0>,
		<&clock_audio_wsa_1 0>, <&clock_audio_va_1 0>,
		<&clock_audio_wsa_2 0>, <&clock_audio_rx_tx 0>,
		<&clock_audio_wsa_tx 0>, <&clock_audio_wsa2_tx 0>;
	};

	va_macro: va-macro@33F0000 {
		compatible = "qcom,lpass-cdc-va-macro";
		reg = <0x33F0000 0x0>;
		clock-names = "lpass_audio_hw_vote";
		clocks = <&lpass_audio_hw_vote 0>;
		qcom,va-dmic-sample-rate = <600000>;
		qcom,va-clk-mux-select = <1>;
		qcom,va-island-mode-muxsel = <0x03420000>;
		qcom,default-clk-id = <TX_CORE_CLK>;
		qcom,is-used-swr-gpio = <1>;
		qcom,va-swr-gpios = <&va_swr_gpios>;
		swr2: va_swr_master {
			compatible = "qcom,swr-mstr";
			#address-cells = <2>;
			#size-cells = <0>;
			clock-names ="lpass_audio_hw_vote";
			clocks = <&lpass_audio_hw_vote 0>;
			qcom,swr_master_id = <3>;
			qcom,mipi-sdw-block-packing-mode = <1>;
			swrm-io-base = <0x33b0000 0x0>;
			interrupts =
				<GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq", "swr_wake_irq";
			qcom,swr-wakeup-required = <1>;
			qcom,swr-num-ports = <3>;
			qcom,swr-port-mapping = <1 SWRM_TX1_CH1 0x1>,
				<1 SWRM_TX1_CH2 0x2>,
				<1 SWRM_TX1_CH3 0x4>, <1 SWRM_TX1_CH4 0x8>,
				<2 SWRM_TX2_CH1 0x1>, <2 SWRM_TX2_CH2 0x2>,
				<2 SWRM_TX2_CH3 0x4>, <2 SWRM_TX2_CH4 0x8>,
				<3 SWRM_TX3_CH1 0x1>, <3 SWRM_TX3_CH2 0x2>,
				<3 SWRM_TX3_CH3 0x4>, <3 SWRM_TX3_CH4 0x8>;
			qcom,swr-num-dev = <5>;
			qcom,swr-clock-stop-mode0 = <1>;
			qcom,swr-mstr-irq-wakeup-capable = <1>;
			qcom,is-always-on = <1>;
			wcd938x_tx_slave: wcd938x-tx-slave {
				compatible = "qcom,wcd938x-slave";
				reg = <0x0D 0x01170223>;
			};
			wcd937x_tx_slave: wcd937x-tx-slave {
				status = "disabled";
				compatible = "qcom,wcd937x-slave";
				reg = <0x0A 0x01170223>;
			};
		};
	};

	tx_macro: tx-macro@3220000 {
		compatible = "qcom,lpass-cdc-tx-macro";
		reg = <0x3220000 0x0>;
		qcom,default-clk-id = <TX_CORE_CLK>;
		qcom,tx-dmic-sample-rate = <2400000>;
		qcom,is-used-swr-gpio = <0>;
	};

	rx_macro: rx-macro@3200000 {
		compatible = "qcom,lpass-cdc-rx-macro";
		reg = <0x3200000 0x0>;
		qcom,rx-swr-gpios = <&rx_swr_gpios>;
		qcom,rx_mclk_mode_muxsel = <0x033A40D8>;
		qcom,rx-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
		qcom,default-clk-id = <RX_TX_CORE_CLK>;
		clock-names = "rx_mclk2_2x_clk";
		clocks = <&clock_audio_rx_mclk2_2x_clk 0>;
		swr1: rx_swr_master {
			compatible = "qcom,swr-mstr";
			#address-cells = <2>;
			#size-cells = <0>;
			clock-names ="lpass_audio_hw_vote";
			clocks = <&lpass_audio_hw_vote 0>;
			qcom,swr_master_id = <2>;
			qcom,mipi-sdw-block-packing-mode = <1>;
			swrm-io-base = <0x3210000 0x0>;
			interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq";
			qcom,swr-num-ports = <6>;
			qcom,swr-port-mapping = <1 HPH_L 0x1>,
				<1 HPH_R 0x2>, <2 CLSH 0x1>,
				<3 COMP_L 0x1>, <3 COMP_R 0x2>,
				<4 LO 0x1>, <5 DSD_L 0x1>,
				<5 DSD_R 0x2>, <6 PCM_OUT1 0x01>;
			qcom,swr-num-dev = <2>;
			qcom,swr-clock-stop-mode0 = <1>;

			wcd938x_rx_slave: wcd938x-rx-slave {
				compatible = "qcom,wcd938x-slave";
				reg = <0x0D 0x01170224>;
			};

			wcd937x_rx_slave: wcd937x-rx-slave {
				status = "disabled";
				compatible = "qcom,wcd937x-slave";
				reg = <0x0A 0x01170224>;
			};
		};
	};

	wsa_macro: wsa-macro@3240000 {
		compatible = "qcom,lpass-cdc-wsa-macro";
		reg = <0x3240000 0x0>;
		qcom,wsa-swr-gpios = <&wsa_swr_gpios>;
		qcom,wsa-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
		qcom,default-clk-id = <WSA_TX_CORE_CLK>;
		qcom,thermal-max-state = <11>;
		#cooling-cells = <2>;
		swr0: wsa_swr_master {
			compatible = "qcom,swr-mstr";
			#address-cells = <2>;
			#size-cells = <0>;
			clock-names ="lpass_audio_hw_vote";
			clocks = <&lpass_audio_hw_vote 0>;
			qcom,swr_master_id = <1>;
			qcom,mipi-sdw-block-packing-mode = <0>;
			swrm-io-base = <0x3250000 0x0>;
			interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq";
			qcom,swr-num-ports = <8>;
			qcom,swr-clock-stop-mode0 = <1>;
			qcom,swr-port-mapping = <1 SPKR_L 0x1>,
				<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
				<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
				<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
				<8 SPKR_R_VI 0x3>;
			qcom,swr-num-dev = <2>;
			qcom,dynamic-port-map-supported = <0>;
			wsa883x_0221: wsa883x@02170221 {
				compatible = "qcom,wsa883x";
				reg = <0x2 0x2170221>;
				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
				qcom,lpass-cdc-handle = <&lpass_cdc>;

				cdc-vdd-1p8-supply = <&L21B>;
				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
				qcom,cdc-vdd-1p8-current = <20000>;
				qcom,cdc-static-supplies = "cdc-vdd-1p8";
				sound-name-prefix = "SpkrLeft";
			};

			wsa883x_0222: wsa883x@02170222 {
				compatible = "qcom,wsa883x";
				reg = <0x2 0x2170222>;
				qcom,spkr-sd-n-node = <&wsa_spkr_en2>;
				qcom,lpass-cdc-handle = <&lpass_cdc>;

				cdc-vdd-1p8-supply = <&L21B>;
				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
				qcom,cdc-vdd-1p8-current = <20000>;
				qcom,cdc-static-supplies = "cdc-vdd-1p8";
				sound-name-prefix = "SpkrRight";
			};

			wsa881x_0213: wsa881x@21170213 {
				status = "disabled";
				compatible = "qcom,wsa881x";
				reg = <0x10 0x21170213>;
				qcom,spkr-sd-n-node = <&wsa_spkr_en1>;
				qcom,lpass-cdc-handle = <&lpass_cdc>;
				wsa_dev_index = <1>;

				cdc-vdd-1p8-supply = <&L21B>;
				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
				qcom,cdc-vdd-1p8-current = <20000>;
				qcom,cdc-static-supplies = "cdc-vdd-1p8";
				sound-name-prefix = "SpkrRight";
			};
		};
	};

	wsa2_macro: wsa2-macro@31E0000 {
		compatible = "qcom,lpass-cdc-wsa2-macro";
		reg = <0x31E0000 0x0>;
		qcom,wsa2-swr-gpios = <&wsa2_swr_gpios>;
		qcom,wsa2-bcl-pmic-params = /bits/ 8 <0x00 0x03 0x48>;
		qcom,default-clk-id = <WSA2_TX_CORE_CLK>;
		qcom,thermal-max-state = <11>;
		#cooling-cells = <2>;
		status = "disabled";
		swr3: wsa2_swr_master {
			compatible = "qcom,swr-mstr";
			#address-cells = <2>;
			#size-cells = <0>;
			clock-names ="lpass_audio_hw_vote";
			clocks = <&lpass_audio_hw_vote 0>;
			qcom,swr_master_id = <4>;
			qcom,mipi-sdw-block-packing-mode = <0>;
			swrm-io-base = <0x31f0000 0x0>;
			interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>;
			interrupt-names = "swr_master_irq";
			qcom,swr-num-ports = <8>;
			qcom,swr-clock-stop-mode0 = <1>;
			qcom,swr-port-mapping = <1 SPKR_L 0x1>,
				<2 SPKR_L_COMP 0xF>, <3 SPKR_L_BOOST 0x3>,
				<4 SPKR_R 0x1>, <5 SPKR_R_COMP 0xF>,
				<6 SPKR_R_BOOST 0x3>, <7 SPKR_L_VI 0x3>,
				<8 SPKR_R_VI 0x3>;
			qcom,swr-num-dev = <2>;
			qcom,dynamic-port-map-supported = <0>;
			wsa883x_2_0221: wsa883x@02170221 {
				compatible = "qcom,wsa883x_2";
				reg = <0x2 0x2170221>;
				qcom,spkr-sd-n-node = <&wsa2_spkr_en1>;
				qcom,lpass-cdc-handle = <&lpass_cdc>;

				cdc-vdd-1p8-supply = <&L21B>;
				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
				qcom,cdc-vdd-1p8-current = <20000>;
				qcom,cdc-static-supplies = "cdc-vdd-1p8";
				sound-name-prefix = "Spkr2Left";
			};

			wsa883x_2_0222: wsa883x@02170222 {
				compatible = "qcom,wsa883x_2";
				reg = <0x2 0x2170222>;
				qcom,spkr-sd-n-node = <&wsa2_spkr_en2>;
				qcom,lpass-cdc-handle = <&lpass_cdc>;

				cdc-vdd-1p8-supply = <&L21B>;
				qcom,cdc-vdd-1p8-voltage = <1800000 1800000>;
				qcom,cdc-vdd-1p8-current = <20000>;
				qcom,cdc-static-supplies = "cdc-vdd-1p8";
				sound-name-prefix = "Spkr2Right";
			};
		};
	};

	wcd937x_codec: wcd937x-codec {
		status = "disabled";
		compatible = "qcom,wcd937x-codec";
		qcom,split-codec = <1>;
		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
			<4 DSD_R 0x2 0 DSD_R>;
		qcom,tx_swr_ch_map = <0 ADC1 0x1 4800000 SWRM_TX1_CH1>,
			<1 ADC2 0x1 4800000 SWRM_TX2_CH1>,
			<1 ADC3 0x2 4800000 SWRM_TX2_CH2>,
			<2 DMIC0 0x1 0 SWRM_TX1_CH4>,
			<2 DMIC1 0x2 0 SWRM_TX2_CH1>,
			<2 MBHC 0x4 4800000 SWRM_TX2_CH2>,
			<3 DMIC2 0x1 0 SWRM_TX2_CH3>,
			<3 DMIC3 0x2 0 SWRM_TX2_CH4>,
			<3 DMIC4 0x4 0 SWRM_TX3_CH1>,
			<3 DMIC5 0x8 0 SWRM_TX3_CH2>;

		qcom,swr-tx-port-params =
			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;

		qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
		qcom,rx-slave = <&wcd937x_rx_slave>;
		qcom,tx-slave = <&wcd937x_tx_slave>;

		cdc-vdd-rxtx-supply = <&L21B>;
		qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
		qcom,cdc-vdd-rxtx-current = <13890>;

		cdc-vddpx-supply = <&L21B>;
		qcom,cdc-vddpx-voltage = <1800000 1800000>;
		qcom,cdc-vddpx-current = <13890>;

		cdc-vdd-buck-supply = <&L20B>;
		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
		qcom,cdc-vdd-buck-current = <361110>;

		qcom,cdc-vdd-mic-bias-voltage = <3700000 3700000>;
		qcom,cdc-vdd-mic-bias-current = <6760>;

		qcom,cdc-micbias1-mv = <1800>;
		qcom,cdc-micbias2-mv = <1800>;
		qcom,cdc-micbias3-mv = <1800>;

		qcom,cdc-static-supplies = "cdc-vdd-rxtx",
					   "cdc-vddpx";
		qcom,cdc-on-demand-supplies = "cdc-vdd-buck";
	};

	wcd938x_codec: wcd938x-codec {
		compatible = "qcom,wcd938x-codec";
		qcom,split-codec = <1>;
		qcom,rx_swr_ch_map = <0 HPH_L 0x1 0 HPH_L>,
			<0 HPH_R 0x2 0 HPH_R>, <1 CLSH 0x1 0 CLSH>,
			<2 COMP_L 0x1 0 COMP_L>, <2 COMP_R 0x2 0 COMP_R>,
			<3 LO 0x1 0 LO>, <4 DSD_L 0x1 0 DSD_L>,
			<4 DSD_R 0x2 0 DSD_R>;

		qcom,tx_swr_ch_map = <0 ADC1 0x1 0 SWRM_TX1_CH1>,
			<0 ADC2 0x2 0 SWRM_TX1_CH2>,
			<1 ADC3 0x1 0 SWRM_TX1_CH3>,
			<1 ADC4 0x2 0 SWRM_TX1_CH4>,
			<2 DMIC0 0x1 0 SWRM_TX2_CH1>,
			<2 DMIC1 0x2 0 SWRM_TX2_CH2>,
			<2 MBHC 0x4 0 SWRM_TX2_CH3>,
			<2 DMIC2 0x4 0 SWRM_TX2_CH3>,
			<2 DMIC3 0x8 0 SWRM_TX2_CH4>,
			<3 DMIC4 0x1 0 SWRM_TX3_CH1>,
			<3 DMIC5 0x2 0 SWRM_TX3_CH2>,
			<3 DMIC6 0x4 0 SWRM_TX3_CH3>,
			<3 DMIC7 0x8 0 SWRM_TX3_CH4>;

		qcom,swr-tx-port-params =
			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL0 LANE2>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>,
			<OFFSET1_VAL0 LANE1>, <OFFSET1_VAL2 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL2 LANE0>,
			<OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>, <OFFSET1_VAL1 LANE0>;

		qcom,wcd-rst-gpio-node = <&wcd_rst_gpio>;
		qcom,rx-slave = <&wcd938x_rx_slave>;
		qcom,tx-slave = <&wcd938x_tx_slave>;

		cdc-vdd-rxtx-supply = <&L21B>;
		qcom,cdc-vdd-rxtx-voltage = <1800000 1800000>;
		qcom,cdc-vdd-rxtx-current = <30000>;

		cdc-vddio-supply = <&L21B>;
		qcom,cdc-vddio-voltage = <1800000 1800000>;
		qcom,cdc-vddio-current = <30000>;

		cdc-vdd-buck-supply = <&L20B>;
		qcom,cdc-vdd-buck-voltage = <1800000 1800000>;
		qcom,cdc-vdd-buck-current = <650000>;

		qcom,cdc-vdd-mic-bias-voltage = <3296000 3296000>;
		qcom,cdc-vdd-mic-bias-current = <30000>;

		qcom,cdc-micbias1-mv = <1800>;
		qcom,cdc-micbias2-mv = <1800>;
		qcom,cdc-micbias3-mv = <1800>;
		qcom,cdc-micbias4-mv = <1800>;

		qcom,cdc-static-supplies = "cdc-vdd-rxtx",
					   "cdc-vddio",
					   "cdc-vdd-buck";
	};

};

&spf_core_platform  {
	waipio_snd: sound {
		qcom,model = "ravelin-idp-snd-card";
		qcom,msm-mi2s-master = <1>, <1>, <1>, <1>, <1>, <1>;
		qcom,mi2s-tdm-is-hw-vote-needed = <1>, <0>, <1>, <0>, <0>, <0>;
		qcom,tdm-max-slots = <8>;
		qcom,wcn-btfm = <1>;
		qcom,tdm-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
		qcom,mi2s-clk-attribute = <0x1>, <0x1>, <0x1>, <0x1>, <0x1>, <0x1>;
		qcom,audio-routing =
			"AMIC1", "Analog Mic1",
			"AMIC1", "MIC BIAS1",
			"AMIC2", "Analog Mic2",
			"AMIC2", "MIC BIAS2",
			"AMIC3", "Analog Mic3",
			"AMIC3", "MIC BIAS3",
			"TX DMIC0", "Digital Mic0",
			"TX DMIC0", "MIC BIAS3",
			"TX DMIC1", "Digital Mic1",
			"TX DMIC1", "MIC BIAS3",
			"TX DMIC2", "Digital Mic2",
			"TX DMIC2", "MIC BIAS1",
			"TX DMIC3", "Digital Mic3",
			"TX DMIC3", "MIC BIAS1",
			"IN1_HPHL", "HPHL_OUT",
			"IN2_HPHR", "HPHR_OUT",
			"IN3_AUX", "AUX_OUT",
			"WSA SRC0_INP", "SRC0",
			"WSA_TX DEC0_INP", "TX DEC0 MUX",
			"WSA_TX DEC1_INP", "TX DEC1 MUX",
			"RX_TX DEC0_INP", "TX DEC0 MUX",
			"RX_TX DEC1_INP", "TX DEC1 MUX",
			"RX_TX DEC2_INP", "TX DEC2 MUX",
			"RX_TX DEC3_INP", "TX DEC3 MUX",
			"SpkrLeft IN", "WSA_SPK1 OUT",
			"SpkrRight IN", "WSA_SPK2 OUT",
			"TX SWR_INPUT", "WCD_TX_OUTPUT",
			"VA SWR_INPUT", "VA_SWR_CLK",
			"VA SWR_INPUT", "WCD_TX_OUTPUT",
			"VA_AIF1 CAP", "VA_SWR_CLK",
			"VA_AIF2 CAP", "VA_SWR_CLK",
			"VA_AIF3 CAP", "VA_SWR_CLK",
			"VA DMIC0", "Digital Mic0",
			"VA DMIC1", "Digital Mic1",
			"VA DMIC2", "Digital Mic2",
			"VA DMIC3", "Digital Mic3",
			"VA DMIC0", "VA MIC BIAS3",
			"VA DMIC1", "VA MIC BIAS3",
			"VA DMIC2", "VA MIC BIAS1",
			"VA DMIC3", "VA MIC BIAS1";
		qcom,msm-mbhc-usbc-audio-supported = <0>;
		qcom,msm-mbhc-hphl-swh = <1>;
		qcom,msm-mbhc-gnd-swh = <1>;

		qcom,cdc-dmic01-gpios = <&cdc_dmic01_gpios>;
		qcom,cdc-dmic23-gpios = <&cdc_dmic23_gpios>;
		qcom,cdc-dmic45-gpios = <&cdc_dmic45_gpios>;
		asoc-codec  = <&stub_codec>, <&lpass_cdc>,
			      <&wcd938x_codec>,
			      <&wsa883x_0221>, <&wsa883x_0222>;
		asoc-codec-names = "msm-stub-codec.1", "lpass-cdc",
				   "wcd938x_codec",
				   "wsa-codec1", "wsa-codec2";
		qcom,wsa-max-devs = <2>;
		qcom,msm_audio_ssr_devs = <&audio_gpr>, <&lpi_tlmm>,
				  <&lpass_cdc>;
		qcom,upd_backends_used = "wcd";
		qcom,upd_lpass_reg_addr = <0x00000418 0x33B0300>;
		qcom,upd_ear_pa_reg_addr = <0x300A>;
	};

	wsa_swr_gpios: wsa_swr_clk_data_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&wsa_swr_clk_active &wsa_swr_data_active>;
		pinctrl-1 = <&wsa_swr_clk_sleep &wsa_swr_data_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	wsa2_swr_gpios: wsa2_swr_clk_data_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&wsa2_swr_clk_active &wsa2_swr_data_active>;
		pinctrl-1 = <&wsa2_swr_clk_sleep &wsa2_swr_data_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	rx_swr_gpios: rx_swr_clk_data_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&rx_swr_clk_active &rx_swr_data_active
				&rx_swr_data1_active>;
		pinctrl-1 = <&rx_swr_clk_sleep &rx_swr_data_sleep
				&rx_swr_data1_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	va_swr_gpios: tx_swr_clk_data_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&tx_swr_clk_active &tx_swr_data0_active
			    &tx_swr_data1_active &tx_swr_data2_active>;
		pinctrl-1 = <&tx_swr_clk_sleep &tx_swr_data0_sleep
			    &tx_swr_data1_sleep &tx_swr_data2_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	cdc_dmic01_gpios: cdc_dmic01_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&cdc_dmic01_clk_active &cdc_dmic01_data_active>;
		pinctrl-1 = <&cdc_dmic01_clk_sleep &cdc_dmic01_data_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	cdc_dmic23_gpios: cdc_dmic23_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&cdc_dmic23_clk_active &cdc_dmic23_data_active>;
		pinctrl-1 = <&cdc_dmic23_clk_sleep &cdc_dmic23_data_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	cdc_dmic45_gpios: cdc_dmic45_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&cdc_dmic45_clk_active &cdc_dmic45_data_active>;
		pinctrl-1 = <&cdc_dmic45_clk_sleep &cdc_dmic45_data_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};

	cdc_dmic67_gpios: cdc_dmic67_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&cdc_dmic67_clk_active &cdc_dmic67_data_active>;
		pinctrl-1 = <&cdc_dmic67_clk_sleep &cdc_dmic67_data_sleep>;
		qcom,lpi-gpios;
		#gpio-cells = <0>;
	};
};

&lpi_tlmm {
	clock-names ="lpass_audio_hw_vote";
	clocks = <&lpass_audio_hw_vote 0>;
};

&lpass_core_hw_vote {
	status = "disabled";
};

&msm_audio_ion {
	iommus = <&apps_smmu 0x1001 0x0>;
};

&va_cdc_dma_0_tx {
	qcom,msm-dai-is-island-supported = <1>;
};

&soc {
	wsa_spkr_en1: wsa_spkr_en1_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&spkr_1_sd_n_active>;
		pinctrl-1 = <&spkr_1_sd_n_sleep>;
	};

	wsa_spkr_en2: wsa_spkr_en2_pinctrl {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&spkr_2_sd_n_active>;
		pinctrl-1 = <&spkr_2_sd_n_sleep>;
	};

	wsa2_spkr_en1: wsa2_spkr_en1_pinctrl {
		status = "disabled";
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&spkr_1_sd_n_active>;
		pinctrl-1 = <&spkr_1_sd_n_sleep>;
	};

	wsa2_spkr_en2: wsa2_spkr_en2_pinctrl {
		status = "disabled";
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&spkr_2_sd_n_active>;
		pinctrl-1 = <&spkr_2_sd_n_sleep>;
	};

	wcd_rst_gpio: msm_cdc_pinctrl@54 {
		compatible = "qcom,msm-cdc-pinctrl";
		pinctrl-names = "aud_active", "aud_sleep";
		pinctrl-0 = <&wcd_reset_active>;
		pinctrl-1 = <&wcd_reset_sleep>;
	};

	clock_audio_va_1: va_core_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x307>;
		#clock-cells = <1>;
	};

	clock_audio_wsa_1: wsa_core_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_2>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x309>;
		#clock-cells = <1>;
	};

	clock_audio_wsa_2: wsa2_core_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_9>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x310>;
		#clock-cells = <1>;
	};

	clock_audio_rx_1: rx_core_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_4>;
		qcom,codec-lpass-ext-clk-freq = <22579200>;
		qcom,codec-lpass-clk-id = <0x30E>;
		#clock-cells = <1>;
	};

	clock_audio_rx_tx: rx_core_tx_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_10>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x312>;
		#clock-cells = <1>;
	};

	clock_audio_tx_1: tx_core_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_6>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x30C>;
		#clock-cells = <1>;
	};

	clock_audio_wsa_tx: wsa_core_tx_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_11>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x314>;
		#clock-cells = <1>;
	};

	clock_audio_wsa2_tx: wsa2_core_tx_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_12>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x316>;
		#clock-cells = <1>;
	};

	clock_audio_rx_mclk2_2x_clk: rx_mclk2_2x_clk {
		compatible = "qcom,audio-ref-clk";
		qcom,codec-ext-clk-src = <AUDIO_LPASS_MCLK_13>;
		qcom,codec-lpass-ext-clk-freq = <19200000>;
		qcom,codec-lpass-clk-id = <0x318>;
		#clock-cells = <1>;
	};
};
