#include <dt-bindings/clock/qcom,gcc-waipio.h>
#include <dt-bindings/phy/qcom,usb3-4nm-qmp-combo.h>

&soc {
	usb0: ssusb@a600000 {
		compatible = "qcom,dwc-usb3-msm";
		reg = <0xa600000 0x100000>;
		reg-names = "core_base";

		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
		clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>,
			<&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
			<&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
			<&clock_gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
			<&clock_gcc GCC_USB30_PRIM_SLEEP_CLK>;
		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
					"utmi_clk", "sleep_clk";

		resets = <&clock_gcc GCC_USB30_PRIM_BCR>;
		reset-names = "core_reset";

		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
			<&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
			<&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
			<&pdc 15 IRQ_TYPE_EDGE_RISING>;
		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
				"ss_phy_irq", "dm_hs_phy_irq";
		qcom,use-pdc-interrupts;
		qcom,use-eusb2-phy;

		qcom,dis-sending-cm-l1-quirk;
		qcom,core-clk-rate = <200000000>;
		qcom,core-clk-rate-disconnected = <133333333>;
		qcom,core-clk-rate-hs = <66666667>;
		qcom,pm-qos-latency = <2>;
		qcom,num-gsi-evt-buffs = <0x3>;
		qcom,gsi-reg-offset =
			<0x0fc /* GSI_GENERAL_CFG */
			0x110 /* GSI_DBL_ADDR_L */
			0x120 /* GSI_DBL_ADDR_H */
			0x130 /* GSI_RING_BASE_ADDR_L */
			0x144 /* GSI_RING_BASE_ADDR_H */
			0x1a4>; /* GSI_IF_STS */

		interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb";
		interconnects = <&aggre1_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>,
				<&aggre1_noc MASTER_USB3_0 &config_noc SLAVE_IPA_CFG>,
				<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_USB3_0>;
		extcon = <&eud>;

		dwc3@a600000 {
			compatible = "snps,dwc3";
			reg = <0xa600000 0xd93c>;

			iommus = <&apps_smmu 0x0 0x0>;
			qcom,iommu-dma = "atomic";
			qcom,iommu-dma-addr-pool = <0x90000000 0x60000000>;
			dma-coherent;

			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
			usb-phy = <&eusb2_phy0>, <&usb_nop_phy>;
			snps,disable-clk-gating;
			snps,has-lpm-erratum;
			snps,hird-threshold = /bits/ 8 <0x0>;
			snps,is-utmi-l1-suspend;
			snps,usb2-gadget-lpm-disable;
			snps,dis-u1-entry-quirk;
			snps,dis-u2-entry-quirk;
			snps,dis_u2_susphy_quirk;
			snps,dis_u3_susphy_quirk;
			snps,ssp-u3-u0-quirk;
			tx-fifo-resize;
			dr_mode = "otg";
			maximum-speed = "high-speed";
		};
	};

	/* USB port related High Speed PHY */
	eusb2_phy0: hsphy@88e3000 {
		compatible = "qcom,usb-snps-eusb2-phy";
		reg = <0x88e3000 0x154>,
			<0x088e2000 0x4>,
			<0x0C276000 0x4>;
		reg-names = "eusb2_phy_base",
			"eud_enable_reg",
			"eud_detect_reg";

		vdd-supply = <&L5B>;
		vdda12-supply = <&L10C>;
		qcom,vdd-voltage-level = <0 880000 880000>;

		clocks = <&clock_rpmh RPMH_CXO_CLK>,
			 <&clock_gcc GCC_EUSB3_0_CLKREF_EN>;
		clock-names = "ref_clk_src", "ref_clk";

		resets = <&clock_gcc GCC_QUSB2PHY_PRIM_BCR>;
		reset-names = "phy_reset";
	};
	usb_nop_phy:usb_nop_phy{
		status = "okay";
		compatible = "usb-nop-xceiv";
	};


	/* USB port related QMP USB DP Combo PHY */
	usb_qmp_dp_phy: ssphy@88e8000 {
		compatible = "qcom,usb-ssphy-qmp-dp-combo";
		reg = <0x88e8000 0x3000>;
		reg-names = "qmp_phy_base";

		status = "disabled";
		vdd-supply = <&L1B>;
		qcom,vdd-voltage-level = <0 912000 912000>;
		qcom,vdd-max-load-uA = <47000>;
		core-supply = <&L10C>;

		clocks = <&clock_gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK>,
			<&clock_gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>,
			<&clock_gcc USB3_PHY_WRAPPER_GCC_USB30_PIPE_CLK>,
			<&clock_rpmh RPMH_CXO_CLK>,
			<&clock_gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
			<&clock_gcc GCC_USB3_0_CLKREF_EN>;
		clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux",
				"pipe_clk_ext_src", "ref_clk_src",
				"com_aux_clk", "ref_clk";

		resets = <&clock_gcc GCC_USB3_DP_PHY_PRIM_BCR>,
			<&clock_gcc GCC_USB3_PHY_PRIM_BCR>;
		reset-names = "global_phy_reset", "phy_reset";

		pinctrl-names = "default";
		pinctrl-0 = <&usb3phy_portselect_default>;

		qcom,qmp-phy-reg-offset =
			<USB3_DP_PCS_PCS_STATUS1
			 USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL
			 USB3_DP_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR
			 USB3_DP_PCS_POWER_DOWN_CONTROL
			 USB3_DP_PCS_SW_RESET
			 USB3_DP_PCS_START_CONTROL
			 0xffff /* USB3_PHY_PCS_MISC_TYPEC_CTRL */
			 USB3_DP_COM_POWER_DOWN_CTRL
			 USB3_DP_COM_SW_RESET
			 USB3_DP_COM_RESET_OVRD_CTRL
			 USB3_DP_COM_PHY_MODE_CTRL
			 USB3_DP_COM_TYPEC_CTRL
			 USB3_DP_PCS_AON_CLAMP_ENABLE>;

		qcom,qmp-phy-init-seq =
			/* <reg_offset, value> */
			<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1                  0x55
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1                   0x0E
			USB3_DP_QSERDES_COM_CP_CTRL_MODE1                          0x02
			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1                        0x16
			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1                        0x36
			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1                      0x04
			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1                        0x2E
			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1                        0x82
			USB3_DP_QSERDES_COM_DEC_START_MODE1                        0x04
			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1                    0x01
			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1                  0x55
			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1                  0xD5
			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1                  0x05
			USB3_DP_QSERDES_COM_HSCLK_SEL_1                            0x01
			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1                        0x25
			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1                        0x02
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1             0xB7
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1             0x1E
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0             0xB7
			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0             0x1E
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0                   0x55
			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0                   0x0E
			USB3_DP_QSERDES_COM_CP_CTRL_MODE0                          0x02
			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0                        0x16
			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0                        0x36
			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0                        0x12
			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0                        0x34
			USB3_DP_QSERDES_COM_DEC_START_MODE0                        0x04
			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0                    0x01
			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0                  0x55
			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0                  0xD5
			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0                  0x05
			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0                        0x25
			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0                        0x02
			USB3_DP_QSERDES_COM_BG_TIMER                               0x0E
			USB3_DP_QSERDES_COM_SSC_EN_CENTER                          0x01
			USB3_DP_QSERDES_COM_SSC_PER1                               0x31
			USB3_DP_QSERDES_COM_SSC_PER2                               0x01
			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE                      0x0C
			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL                          0x1A
			USB3_DP_QSERDES_COM_LOCK_CMP_CFG                           0x14
			USB3_DP_QSERDES_COM_VCO_TUNE_MAP                           0x04
			USB3_DP_QSERDES_COM_CORE_CLK_EN                            0x20
			USB3_DP_QSERDES_COM_CMN_CONFIG_1                           0x04
			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1                   0xB6
			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2                   0x4B
			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3                   0x37
			USB3_DP_QSERDES_COM_ADDITIONAL_MISC                        0x0C
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX                       0x00
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX                       0x00
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX                0x1F
			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX                0x09
			USB3_DP_QSERDES_TXA_LANE_MODE_1                            0xF5
			USB3_DP_QSERDES_TXA_LANE_MODE_3                            0x3F
			USB3_DP_QSERDES_TXA_LANE_MODE_4                            0x3F
			USB3_DP_QSERDES_TXA_LANE_MODE_5                            0x5F
			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2                       0x12
			USB3_DP_QSERDES_TXA_PI_QEC_CTRL                            0x21
			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN                           0x0A
			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN                           0x06
			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN                  0x2F
			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE          0x7F
			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW                0xFF
			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH               0x0F
			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS                       0x99
			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1                       0x08
			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2                       0x08
			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1                         0x00
			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2                         0x08
			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE                 0xA0
			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1                         0x54
			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2                         0x0F
			USB3_DP_QSERDES_RXA_GM_CAL                                 0x13
			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2                  0x0F
			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3                  0x4A
			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4                  0x0A
			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW                    0x07
			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH                   0x00
			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1            0x47
			USB3_DP_QSERDES_RXA_SIGDET_CNTRL                           0x04
			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL                  0x0E
			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW                         0x3F
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH                        0xFF
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2                       0xFF
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3                       0xDF
			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4                       0xFE
			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW                         0xDC
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH                        0x5C
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2                       0x9C
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3                       0x1D
			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4                       0x09
			USB3_DP_QSERDES_RXA_DFE_EN_TIMER                           0x04
			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET               0x38
			USB3_DP_QSERDES_RXA_DCC_CTRL1                              0x0C
			USB3_DP_QSERDES_RXA_VTH_CODE                               0x10
			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1                       0x14
			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM                        0x08
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX                       0x00
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX                       0x00
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX                0x1F
			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX                0x09
			USB3_DP_QSERDES_TXB_LANE_MODE_1                            0xF5
			USB3_DP_QSERDES_TXB_LANE_MODE_3                            0x3F
			USB3_DP_QSERDES_TXB_LANE_MODE_4                            0x3F
			USB3_DP_QSERDES_TXB_LANE_MODE_5                            0x5F
			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2                       0x12
			USB3_DP_QSERDES_TXB_PI_QEC_CTRL                            0x05
			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN                           0x0A
			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN                           0x06
			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN                  0x2F
			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE          0x7F
			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW                0xFF
			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH               0x0F
			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS                       0x99
			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1                       0x08
			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2                       0x08
			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1                         0x00
			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2                         0x08
			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE                 0xA0
			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1                         0x54
			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2                         0x0F
			USB3_DP_QSERDES_RXB_GM_CAL                                 0x13
			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2                  0x0F
			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3                  0x4A
			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4                  0x0A
			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW                    0x07
			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH                   0x00
			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1            0x47
			USB3_DP_QSERDES_RXB_SIGDET_CNTRL                           0x04
			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL                  0x0E
			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW                         0x3F
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH                        0xFF
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2                       0xFF
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3                       0xDF
			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4                       0xFE
			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW                         0xDC
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH                        0x5C
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2                       0x9C
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3                       0x1D
			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4                       0x09
			USB3_DP_QSERDES_RXB_DFE_EN_TIMER                           0x04
			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET               0x38
			USB3_DP_QSERDES_RXB_DCC_CTRL1                              0x0C
			USB3_DP_QSERDES_RXB_VTH_CODE                               0x10
			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1                       0x14
			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM                        0x08
			USB3_DP_PCS_LOCK_DETECT_CONFIG1                            0xC4
			USB3_DP_PCS_LOCK_DETECT_CONFIG2                            0x89
			USB3_DP_PCS_LOCK_DETECT_CONFIG3                            0x20
			USB3_DP_PCS_LOCK_DETECT_CONFIG6                            0x13
			USB3_DP_PCS_REFGEN_REQ_CONFIG1                             0x21
			USB3_DP_PCS_RX_SIGDET_LVL                                  0x99
			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L                           0xE7
			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H                           0x03
			USB3_DP_PCS_CDR_RESET_TIME                                 0x0A
			USB3_DP_PCS_ALIGN_DETECT_CONFIG1                           0x88
			USB3_DP_PCS_ALIGN_DETECT_CONFIG2                           0x13
			USB3_DP_PCS_PCS_TX_RX_CONFIG                               0x0C
			USB3_DP_PCS_EQ_CONFIG1                                     0x4B
			USB3_DP_PCS_EQ_CONFIG5                                     0x10
			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL                   0xF8
			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2                  0x07
			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L                        0x40
			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H                        0x00>;
	};

	usb_nop_phy: usb_nop_phy {
		compatible = "usb-nop-xceiv";
	};

	usb_audio_qmi_dev {
		compatible = "qcom,usb-audio-qmi-dev";
		iommus = <&apps_smmu 0x180f 0x0>;
		qcom,iommu-dma = "disabled";
		qcom,usb-audio-stream-id = <0xf>;
		qcom,usb-audio-intr-num = <2>;
	};
};
