#include <dt-bindings/clock/qcom,rpmh.h>
#include <dt-bindings/clock/qcom,camcc-anorak.h>
#include <dt-bindings/clock/qcom,dispcc-anorak.h>
#include <dt-bindings/clock/qcom,gcc-anorak.h>
#include <dt-bindings/clock/qcom,gpucc-anorak.h>
#include <dt-bindings/clock/qcom,videocc-anorak.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interconnect/qcom,icc.h>
#include <dt-bindings/interconnect/qcom,anorak.h>
#include <dt-bindings/soc/qcom,ipcc.h>
#include <dt-bindings/soc/qcom,rpmh-rsc.h>
#include <dt-bindings/gpio/gpio.h>
#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/spmi/spmi.h>
#include <dt-bindings/power/qcom-aoss-qmp.h>
#include <dt-bindings/clock/qcom,aop-qmp.h>

/ {
	model = "Qualcomm Technologies, Inc. Anorak";
	compatible = "qcom,anorak";
	qcom,msm-id = <549 0x10000>;
	interrupt-parent = <&intc>;

	#address-cells = <2>;
	#size-cells = <2>;
	memory { device_type = "memory"; reg = <0 0 0 0>; };


	chosen: chosen {
		bootargs = "console=ttyMSM0,115200n8 loglevel=6 log_buf_len=256K kernel.panic_on_rcu_stall=1 loop.max_part=7 pcie_ports=compat service_locator.enable=1 msm_rtb.filter=0x237 allow_mismatched_32bit_el0 kasan=off rcupdate.rcu_expedited=1 rcu_nocbs=0-5 ftrace_dump_on_oops pstore.compress=none kpti=off swiotlb=noforce cgroup.memory=nokmem,nosocket allow_file_spec_access can.stats_timer=0 disable_dma32=on cpufreq.default_governor=performance kswapd_per_node=2";
	};

	ddr-regions { };

	reserved_memory: reserved-memory { };

	aliases: aliases {
		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
		mmc1 = &sdhc_2; /* SDC2 SD card slot */
		serial0 = &qupv3_se6_2uart;
		hsuart0 = &qupv3_se5_4uart;
	};

	cpus {
		#address-cells = <2>;
		#size-cells = <0>;

		CPU0: cpu@0 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x0>;
			cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD0>;
			power-domain-names = "psci";
			enable-method = "psci";
			next-level-cache = <&L2_0>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 0 2>;
			L2_0: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;

				L3_0: l3-cache {
					compatible = "arm,arch-cache";
					cache-level = <3>;
				};
			};
		};

		CPU1: cpu@100 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x100>;
			enable-method = "psci";
			cpu-idle-states = <&GOLD_CPU_OFF &GOLD_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD1>;
			power-domain-names = "psci";
			next-level-cache = <&L2_1>;
			capacity-dmips-mhz = <1024>;
			dynamic-power-coefficient = <100>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 0 2>;
			L2_1: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

		};

		CPU2: cpu@200 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x200>;
			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD2>;
			power-domain-names = "psci";
			enable-method = "psci";
			next-level-cache = <&L2_2>;
			capacity-dmips-mhz = <1075>;
			dynamic-power-coefficient = <109>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_2: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};
		};

		CPU3: cpu@300 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x300>;
			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD3>;
			power-domain-names = "psci";
			enable-method = "psci";
			next-level-cache = <&L2_3>;
			capacity-dmips-mhz = <1075>;
			dynamic-power-coefficient = <109>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_3: l2-cache {
			      compatible = "arm,arch-cache";
			      cache-level = <2>;
			      next-level-cache = <&L3_0>;
			};

		};

		CPU4: cpu@400 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x400>;
			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD4>;
			power-domain-names = "psci";
			enable-method = "psci";
			next-level-cache = <&L2_4>;
			capacity-dmips-mhz = <1075>;
			dynamic-power-coefficient = <109>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_4: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
				next-level-cache = <&L3_0>;
			};
		};

		CPU5: cpu@500 {
			device_type = "cpu";
			compatible = "qcom,kryo";
			reg = <0x0 0x500>;
			cpu-idle-states = <&GOLD_PLUS_CPU_OFF &GOLD_PLUS_CPU_RAIL_OFF>;
			power-domains = <&CPU_PD5>;
			power-domain-names = "psci";
			enable-method = "psci";
			next-level-cache = <&L2_5>;
			capacity-dmips-mhz = <1075>;
			dynamic-power-coefficient = <109>;
			#cooling-cells = <2>;
			qcom,freq-domain = <&cpufreq_hw 1 4>;
			L2_5: l2-cache {
				compatible = "arm,arch-cache";
				cache-level = <2>;
				next-level-cache = <&L3_0>;
			};
		};

		cpu-map {
			cluster0 {
				core0 {
					cpu = <&CPU0>;
				};

				core1 {
					cpu = <&CPU1>;
				};
			};

			cluster1 {
				core0 {
					cpu = <&CPU2>;
				};

				core1 {
					cpu = <&CPU3>;
				};

				core2 {
					cpu = <&CPU4>;
				};

				core3 {
					cpu = <&CPU5>;
				};
			};
		};
	};

	idle-states {
		GOLD_CPU_OFF: gold-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <400>;
			exit-latency-us = <1400>;
			min-residency-us = <2207>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_CPU_RAIL_OFF: gold-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <600>;
			exit-latency-us = <1300>;
			min-residency-us = <8136>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		GOLD_PLUS_CPU_OFF: gold-plus-c3 {  /* C3 */
			compatible = "arm,idle-state";
			idle-state-name = "pc";
			entry-latency-us = <300>;
			exit-latency-us = <1450>;
			min-residency-us = <3230>;
			arm,psci-suspend-param = <0x40000003>;
			local-timer-stop;
		};

		GOLD_PLUS_CPU_RAIL_OFF: gold-plus-c4 {  /* C4 */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <500>;
			exit-latency-us = <1350>;
			min-residency-us = <7480>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_PWR_DN: cluster-d4 { /* D4 */
			compatible = "domain-idle-state";
			idle-state-name = "l3-off";
			entry-latency-us = <1050>;
			exit-latency-us = <2500>;
			min-residency-us = <9309>;
			arm,psci-suspend-param = <0x41000044>;
		};

		APSS_OFF: cluster-e3 { /* E3 */
			compatible = "domain-idle-state";
			idle-state-name = "llcc-off";
			entry-latency-us = <2700>;
			exit-latency-us = <3500>;
			min-residency-us = <13959>;
			arm,psci-suspend-param = <0x4100c344>;
		};
	};

	soc: soc { };

	sram: sram@17D09100 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "mmio-sram";
		reg = <0x0 0x17D09100 0x0 0x200>;
		ranges = <0x0 0x0 0x0 0x17D09100 0x0 0x200>;

		cpu_scp_lpri: scp-shmem@0 {
			compatible = "arm,scp-shmem";
			reg = <0x0 0x0 0x0 0x200>;
		};
	};

	firmware: firmware { };
};

#include "anorak-reserved-memory.dtsi"

&reserved_memory {
	#address-cells = <2>;
	#size-cells = <2>;
	ranges;

	/* global autoconfigured region for contiguous allocations */
	system_cma: linux,cma {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
		linux,cma-default;
	};

	user_contig_mem: user_contig_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	qseecom_mem: qseecom_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1400000>;
	};

	qseecom_ta_mem: qseecom_ta_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	cdsp_eva_mem: cdsp_eva_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x400000>;
	};

	adsp_mem_heap: adsp_heap_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0xC00000>;
	};

	cdsp_secure_heap: secure_cdsp_region { /* Secure DSP */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2800000>;
	};

	sp_mem: sp_region {  /* SPSS-HLOS ION shared mem */
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x1000000>;
	};

	ramoops_mem: ramoops_region {
		compatible = "ramoops";
		alloc-ranges = <0x0 0x00000000 0xffffffff 0xffffffff>;
		size = <0x0 0x200000>;
		pmsg-size = <0x200000>;
		mem-type = <2>;
	};

	va_md_mem: va_md_mem_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x1 0x00000000 0xfffffffe 0xffffffff>;
		reusable;
		size = <0 0x1000000>;
	};

	audio_cma_mem: audio_cma_region {
	compatible = "shared-dma-pool";
	alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
	reusable;
	alignment = <0x0 0x400000>;
	size = <0x0 0x1000000>;
	};

	non_secure_display_memory: non_secure_display_region {
		compatible = "shared-dma-pool";
		reusable;
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		size = <0x0 0xa400000>;
		alignment = <0x0 0x400000>;
	};

	cnss_wlan_mem: cnss_wlan_region {
		compatible = "shared-dma-pool";
		alloc-ranges = <0x0 0x00000000 0x0 0xffffffff>;
		reusable;
		alignment = <0x0 0x400000>;
		size = <0x0 0x2000000>;
	};
};

&firmware {
	qcom_scm {
		compatible = "qcom,scm";
		qcom,dload-mode = <&tcsr 0x13000>;
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
	};

	qcom_smcinvoke {
		compatible = "qcom,smcinvoke";
	};

	android {
		compatible = "android,firmware";
		vbmeta {
			compatible = "android,vbmeta";
			parts = "vbmeta,boot,system,vendor,dtbo,recovery";
		};

		fstab {
			compatible = "android,fstab";
			vendor {
				compatible = "android,vendor";
				dev = "/dev/block/platform/soc/1d84000.ufshc/by-name/vendor";
				type = "ext4";
				mnt_flags = "ro,barrier=1,discard";
				fsmgr_flags = "wait,slotselect,avb";
				status = "ok";
			};
		};
	};
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";

		CPU_PD0: cpu-pd0 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD1: cpu-pd1 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD2: cpu-pd2 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD3: cpu-pd3 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD4: cpu-pd4 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CPU_PD5: cpu-pd5 {
			#power-domain-cells = <0>;
			power-domains = <&CLUSTER_PD>;
		};

		CLUSTER_PD: cluster-pd {
			#power-domain-cells = <0>;
			domain-idle-states = <&CLUSTER_PWR_DN &APSS_OFF>;
		};
	};

	slimbam: bamdma@3304000 {
		compatible = "qcom,bam-v1.7.0";
		qcom,controlled-remotely;
		reg = <0x3304000 0x20000>, <0x326b000 0x1000>;
		reg-names = "bam", "bam_remote_mem";
		num-channels  = <31>;
		interrupts = <0 164 IRQ_TYPE_LEVEL_HIGH>;
		#dma-cells = <1>;
		qcom,ee = <1>;
		qcom,num-ees = <2>;
	};

	slim_msm: slim@3340000 {
		compatible = "qcom,slim-ngd-v1.5.0";
		reg = <0x3340000 0x2C000>, <0x326a000 0x1000>;
		reg-names = "ctrl", "slimbus_remote_mem";
		interrupts = <0 163 IRQ_TYPE_LEVEL_HIGH>;
		qcom,apps-ch-pipes = <0x0>;
		qcom,ea-pc = <0x480>;
		dmas = <&slimbam 3>, <&slimbam 4>;
		dma-names = "rx", "tx";
		#address-cells = <1>;
		#size-cells = <0>;
		status = "ok";

		ngd@1 {
			reg = <1>;
			#address-cells = <1>;
			#size-cells = <1>;

			/* slimbus child nodes */
			slimbus: btfmslim-driver {
				compatible = "slim217,221";
				reg = <1 0>;
			};
		};
	};

	intc: interrupt-controller@17200000 {
		compatible = "arm,gic-v3";
		#interrupt-cells = <3>;
		interrupt-controller;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x20000>;
		reg = <0x17200000 0x10000>,	/* GICD */
		      <0x17260000 0x100000>;	/* GICR * 8 */
		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
	};

	cluster-device {
		compatible = "qcom,lpm-cluster-dev";
		power-domains = <&CLUSTER_PD>;
	};

	cpu_pmu: cpu-pmu {
		compatible = "arm,armv8-pmuv3";
		interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>;
	};

	pdc: interrupt-controller@b220000 {
		compatible = "qcom,pdc";
		reg = <0xb220000 0x30000>, <0x174000f0 0x64>;
		reg-names = "pdc-interrupt-base", "apss-shared-spi-cfg";
		qcom,pdc-ranges = <0 480 94>, <94 609 31>, <125 63 1>,
				  <126 716 12>;
		#interrupt-cells = <2>;
		interrupt-parent = <&intc>;
		interrupt-controller;
	};

	cpufreq_hw: qcom,cpufreq-hw {
		compatible = "qcom,cpufreq-hw-epss";
		reg = <0x17d91000 0x1000>,
			<0x17d92000 0x1000>;
		reg-names = "freq-domain0", "freq-domain1";
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>;
		clock-names = "xo", "alternate";
		qcom,lut-row-size = <4>;
		qcom,skip-enable-check;
		qcom,perf-lock-support;
		interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "dcvsh0_int", "dcvsh1_int";
		#freq-domain-cells = <2>;
	};

	qcom,cpufreq-hw-debug {
		compatible = "qcom,cpufreq-hw-epss-debug";
		qcom,freq-hw-domain = <&cpufreq_hw 0>, <&cpufreq_hw 1>;
	};

	apps_rsc: rsc@17a00000 {
		label = "apps_rsc";
		compatible = "qcom,rpmh-rsc";
		reg = <0x17a00000 0x10000>,
		      <0x17a10000 0x10000>,
		      <0x17a20000 0x10000>,
		      <0x17a30000 0x10000>;
		reg-names = "drv-0", "drv-1", "drv-2", "drv-3";
		interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
			     /* No interrupt into GIC for DRV3 */
		qcom,tcs-offset = <0xd00>;
		qcom,drv-id = <2>;
		qcom,tcs-config = <ACTIVE_TCS    3>,
				  <SLEEP_TCS     2>,
				  <WAKE_TCS      2>,
				  <FAST_PATH_TCS 1>,
				  <CONTROL_TCS   0>; /* PDC wakeup values will be written from TZ */
		power-domains = <&CLUSTER_PD>;

		rpmhcc: qcom,rpmhclk {
			compatible = "qcom,anorak-rpmh-clk";
			#clock-cells = <1>;
	};

		apps_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
		};

		dcvs_fp: qcom,dcvs-fp {
			compatible = "qcom,dcvs-fp";
			qcom,ddr-bcm-name = "MC3";
			qcom,llcc-bcm-name = "SH5";
		};
	};

	disp_rsc_0: rsc@af20000 {
		label = "disp_rsc_0";
		compatible = "qcom,rpmh-rsc";
		reg = <0xaf20000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <ACTIVE_TCS    0>,
				  <SLEEP_TCS     1>,
				  <WAKE_TCS      1>,
				  <CONTROL_TCS   0>,
				  <FAST_PATH_TCS 0>;

		disp0_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
		};
	};

	disp_rsc_1: rsc@15720000 {
		label = "disp_rsc_1";
		compatible = "qcom,rpmh-rsc";
		reg = <0x15720000 0x10000>;
		reg-names = "drv-0";
		interrupts = <GIC_SPI 218 IRQ_TYPE_LEVEL_HIGH>;
		qcom,tcs-offset = <0x1c00>;
		qcom,drv-id = <0>;
		qcom,tcs-config = <ACTIVE_TCS    0>,
				  <SLEEP_TCS     1>,
				  <WAKE_TCS      1>,
				  <CONTROL_TCS   0>,
				  <FAST_PATH_TCS 0>;

		disp1_bcm_voter: bcm_voter {
			compatible = "qcom,bcm-voter";
			qcom,tcs-wait = <QCOM_ICC_TAG_AMC>;
		};
	};

	soc-sleep-stats@c3f0000 {
		compatible = "qcom,rpmh-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ss-name = "modem", "adsp", "adsp_island",
			  "cdsp", "slpi", "slpi_island",
			  "apss";
		mboxes = <&qmp_aop 0>;
		ddr-freq-update;
	};

	sys-pm-vx@c320000 {
		compatible = "qcom,sys-pm-violators", "qcom,sys-pm-anorak";
		reg = <0xc320000 0x0400>;
		mboxes = <&qmp_aop 0>;
		mbox-names = "aop";
	};

	cpuss-sleep-stats@17800054 {
		compatible = "qcom,cpuss-sleep-stats-v3";
		reg = <0x17800054 0x4>, <0x17810054 0x4>, <0x17820054 0x4>,
		      <0x17830054 0x4>, <0x17840054 0x4>, <0x17850054 0x4>,
		      <0x17880098 0x4>, <0x178C0000 0x10000>;
		reg-names = "seq_lpm_cntr_cfg_cpu0", "seq_lpm_cntr_cfg_cpu1",
			    "seq_lpm_cntr_cfg_cpu2", "seq_lpm_cntr_cfg_cpu3",
			    "seq_lpm_cntr_cfg_cpu4", "seq_lpm_cntr_cfg_cpu5",
			    "l3_seq_lpm_cntr_cfg", "apss_seq_mem_base";
		num-cpus = <6>;
	};

	subsystem-sleep-stats@c3f0000 {
		compatible = "qcom,subsystem-sleep-stats";
		reg = <0xc3f0000 0x400>;
		ddr-freq-update;
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	kryo-erp {
		compatible = "arm,arm64-kryo-cpu-erp";
		interrupts = <GIC_PPI 0 IRQ_TYPE_LEVEL_HIGH>,
			     <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "l1-l2-faultirq", "l3-scu-faultirq";
	};

	memtimer: timer@17420000 {
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;
		compatible = "arm,armv7-timer-mem";
		reg = <0x17420000 0x1000>;
		clock-frequency = <19200000>;

		frame@17421000 {
			frame-number = <0>;
			interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>,
				     <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17421000 0x1000>,
			      <0x17422000 0x1000>;
		};

		frame@17423000 {
			frame-number = <1>;
			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17423000 0x1000>;
			status = "disabled";
		};

		frame@17425000 {
			frame-number = <2>;
			interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17425000 0x1000>;
			status = "disabled";
		};

		frame@17427000 {
			frame-number = <3>;
			interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17427000 0x1000>;
			status = "disabled";
		};

		frame@17429000 {
			frame-number = <4>;
			interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x17429000 0x1000>;
			status = "disabled";
		};

		frame@1742b000 {
			frame-number = <5>;
			interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742b000 0x1000>;
			status = "disabled";
		};

		frame@1742d000 {
			frame-number = <6>;
			interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
			reg = <0x1742d000 0x1000>;
			status = "disabled";
		};
	};

	qcom,msm-imem@146aa000 {
		compatible = "qcom,msm-imem";
		reg = <0x146aa000 0x1000>;
		ranges = <0x0 0x146aa000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;

		mem_dump_table@10  {
			compatible = "qcom,msm-imem-mem_dump_table";
			reg = <0x10 0x8>;
		};

		restart_reason@65c {
			compatible = "qcom,msm-imem-restart_reason";
			reg = <0x65c 0x4>;
		};

		dload_type@1c {
			compatible = "qcom,msm-imem-dload-type";
			reg = <0x1c 0x4>;
		};

		boot_stats@6b0 {
			compatible = "qcom,msm-imem-boot_stats";
			reg = <0x6b0 0x20>;
		};

		kaslr_offset@6d0 {
			compatible = "qcom,msm-imem-kaslr_offset";
			reg = <0x6d0 0xc>;
		};


		pil@94c {
			compatible = "qcom,pil-reloc-info";
			reg = <0x94c 0xc8>;
		};

		pil@6dc {
			compatible = "qcom,msm-imem-pil-disable-timeout";
			reg = <0x6dc 0x4>;
		};

		diag_dload@c8 {
			compatible = "qcom,msm-imem-diag-dload";
			reg = <0xc8 0xc8>;
		};
	};

	/* PIL spss node - for loading Secure Processor */
	spss_pas: remoteproc-spss@1880000 {
		compatible = "qcom,anorak-spss-pas";
		ranges;
		reg = <0x188101c 0x4>,
		      <0x1881024 0x4>,
		      <0x1881028 0x4>,
		      <0x188103c 0x4>,
		      <0x1881100 0x4>,
		      <0x1882014 0x4>;
		reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", "sp2soc_irq_mask",
			    "rmb_err", "rmb_general_purpose", "rmb_err_spare2";
		interrupts = <0 352 1>;

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";
		qcom,proxy-clock-names = "xo";
		status = "ok";

		memory-region = <&spss_region_mem>;
		qcom,spss-scsr-bits = <24 25>;
		qcom,extra-size = <4096>;

		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "crypto_ddr";

		glink-edge {
			qcom,remote-pid = <8>;
			mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS
				  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "spss_spss";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_SPSS
				      IPCC_MPROC_SIGNAL_GLINK_QMP
				      IRQ_TYPE_EDGE_RISING>;

			reg = <0x1885008 0x8>,
			      <0x1885010 0x4>;
			reg-names = "qcom,spss-addr",
				    "qcom,spss-size";

			label = "spss";
			qcom,glink-label = "spss";
		};
	};

	qcom,spcom {
		compatible = "qcom,spcom";

		qcom,rproc-handle = <&spss_pas>;
		qcom,boot-enabled;
		/* predefined channels, remote side is server */
		qcom,spcom-ch-names = "sp_kernel", "sp_ssr";
		/* sp2soc rmb shared register physical address and bmsk */
		qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>;
		qcom,spcom-sp2soc-rmb-initdone-bit = <24>;
		qcom,spcom-sp2soc-rmb-pbldone-bit = <25>;
		/* soc2sp rmb shared register physical address */
		qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>;
		qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>;
		status = "ok";
	};

	spss_utils: qcom,spss_utils {
		compatible = "qcom,spss-utils";
		/* spss fuses physical address */
		qcom,rproc-handle = <&spss_pas>;
		qcom,spss-fuse1-addr = <0x221C8214>;
		qcom,spss-fuse1-bit = <8>;
		qcom,spss-fuse2-addr = <0x221C8214>;
		qcom,spss-fuse2-bit = <7>;
		qcom,spss-dev-firmware-name  = "spss1d.mdt";  /* 8 chars max */
		qcom,spss-test-firmware-name = "spss1t.mdt";  /* 8 chars max */
		qcom,spss-prod-firmware-name = "spss1p.mdt";  /* 8 chars max */
		qcom,spss-debug-reg-addr = <0x01886020>;
		qcom,spss-debug-reg-addr1 = <0x01888020>;
		qcom,spss-debug-reg-addr3 = <0x0188C020>;
		qcom,spss-emul-type-reg-addr = <0x01fc8004>;
		pil-mem = <&spss_region_mem>;
		qcom,pil-size = <0x0F0000>; // padding to 960KB
		status = "ok";
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,anorak-pinctrl";
		reg = <0xf000000 0x1000000>;
		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		wakeup-parent = <&pdc>;
	};

	dload_mode {
		compatible = "qcom,dload-mode";
	};

	mini_dump_mode {
		compatible = "qcom,minidump";
		status = "ok";
	};

	va_mini_dump {
		compatible = "qcom,va-minidump";
		memory-region = <&va_md_mem>;
		status = "ok";
	};

	clocks {
		xo_board: xo_board {
			compatible = "fixed-clock";
			clock-frequency = <76800000>;
			clock-output-names = "xo_board";
			#clock-cells = <0>;
		};

		sleep_clk: sleep_clk {
			compatible = "fixed-clock";
			clock-frequency = <32000>;
			clock-output-names = "sleep_clk";
			#clock-cells = <0>;
		};

		pcie_0_pipe_clk: pcie_0_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_0_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_1_pipe_clk: pcie_1_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_1_pipe_clk";
			#clock-cells = <0>;
		};

		pcie_2_phy_aux_clk: pcie_2_phy_aux_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_2_phy_aux_clk";
			#clock-cells = <0>;
		};

		pcie_2_pipe_clk: pcie_2_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "pcie_2_pipe_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_0_clk: ufs_phy_rx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_0_clk";
			#clock-cells = <0>;
		};

		ufs_phy_rx_symbol_1_clk: ufs_phy_rx_symbol_1_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_rx_symbol_1_clk";
			#clock-cells = <0>;
		};

		ufs_phy_tx_symbol_0_clk: ufs_phy_tx_symbol_0_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "ufs_phy_tx_symbol_0_clk";
			#clock-cells = <0>;
		};

		usb3_phy_wrapper_gcc_usb30_pipe_clk: usb3_phy_wrapper_gcc_usb30_pipe_clk {
			compatible = "fixed-clock";
			clock-frequency = <1000>;
			clock-output-names = "usb3_phy_wrapper_gcc_usb30_pipe_clk";
			#clock-cells = <0>;
		};
	};

	cache-controller@19e00000 {
		compatible = "qcom,anorak-llcc", "qcom,llcc-v41";
		reg = <0x19e00000 0x800000>, <0x1a600000 0x200000>;
		reg-names = "llcc_base", "llcc_broadcast_base";
		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
		cap-based-alloc-and-pwr-collapse;

		llcc-perfmon {
			compatible = "qcom,llcc-perfmon";
			clocks = <&aoss_qmp QDSS_CLK>;
			clock-names = "qdss_clk";
		};
	};

	hyp_core_ctl: qcom,hyp-core-ctl {
		compatible = "qcom,hyp-core-ctl";
		status = "ok";
	};

	apsscc: syscon@17aa0000 {
		compatible = "syscon";
		reg = <0x17aa0000 0x1c>;
	};

	mccc: syscon@190ba000 {
		compatible = "syscon";
		reg = <0x190ba000 0x54>;
	};

	debugcc: debug-clock-controller@0 {
		compatible = "qcom,anorak-debugcc";
		qcom,gcc = <&gcc>;
		qcom,videocc = <&videocc>;
		qcom,camcc = <&camcc>;
		qcom,gpucc = <&gpucc>;
		qcom,dispcc0 = <&dispcc0>;
		qcom,dispcc1 = <&dispcc1>;
		qcom,apsscc = <&apsscc>;
		qcom,mccc = <&mccc>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc 0>,
			<&camcc 0>,
			<&dispcc0 0>,
			<&dispcc1 0>,
			<&gpucc 0>,
			<&videocc 0>;
		clock-names = "xo_clk_src",
			"gcc",
			"camcc",
			"dispcc0",
			"dispcc1",
			"gpucc",
			"videocc";
		#clock-cells = <1>;
	};

	camcc: clock-controller@ade0000 {
		compatible = "qcom,anorak-camcc", "syscon";
		reg = <0xade0000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&sleep_clk>,
			<&gcc GCC_CAMERA_AHB_CLK>;
		clock-names = "bi_tcxo",
			"sleep_clk","iface";
		clock-output-names = "camcc_clocks";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc0: clock-controller@af00000 {
		compatible = "qcom,anorak-dispcc0", "syscon";
		reg = <0xaf00000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&rpmhcc RPMH_CXO_CLK_A>,
			<&sleep_clk>,
			<&gcc GCC_DISP_AHB_CLK>;
		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	dispcc1: clock-controller@15700000 {
		compatible = "qcom,anorak-dispcc1", "syscon";
		reg = <0x15700000 0x20000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&rpmhcc RPMH_CXO_CLK_A>,
			<&sleep_clk>,
			<&gcc GCC_DISP1_AHB_CLK>;
		clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", "iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gcc: clock-controller@100000 {
		compatible = "qcom,anorak-gcc", "syscon";
		reg = <0x100000 0x1f4200>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>,
			<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
			<&pcie_2_phy_aux_clk>, <&pcie_2_pipe_clk>,
			<&ufs_phy_rx_symbol_0_clk>, <&ufs_phy_rx_symbol_1_clk>,
			<&ufs_phy_tx_symbol_0_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
		clock-names = "bi_tcxo", "sleep_clk",
			"pcie_0_pipe_clk", "pcie_1_pipe_clk",
			"pcie_2_phy_aux_clk", "pcie_2_pipe_clk",
			"ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk",
			"ufs_phy_tx_symbol_0_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	gpucc: clock-controller@3d90000 {
		compatible = "qcom,anorak-gpucc", "syscon";
		reg = <0x3d90000 0xa000>;
		reg-name = "cc_base";
		vdd_cx-supply = <&VDD_CX_LEVEL>;
		vdd_mxa-supply = <&VDD_MXA_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPU_GPLL0_CLK_SRC>,
			<&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>;
		clock-names = "bi_tcxo", "gpll0_out_main",
			"gpll0_out_main_div";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	videocc: clock-controller@aaf0000 {
		compatible = "qcom,anorak-videocc", "syscon";
		reg = <0xaaf0000 0x10000>;
		reg-name = "cc_base";
		vdd_mm-supply = <&VDD_MM_LEVEL>;
		vdd_mxc-supply = <&VDD_MXC_LEVEL>;
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&sleep_clk>,
			<&gcc GCC_VIDEO_AHB_CLK>;
		clock-names = "bi_tcxo", "sleep_clk",
			"iface";
		#clock-cells = <1>;
		#reset-cells = <1>;
	};

	qcom,mpm2-sleep-counter@c221000 {
		compatible = "qcom,mpm2-sleep-counter";
		reg = <0xc221000 0x1000>;
		clock-frequency = <32768>;
	};

	adsp_pas: remoteproc-adsp@03000000 {
		compatible = "qcom,anorak-adsp-pas";
		reg = <0x03000000 0x10000>;

		cx-supply = <&VDD_LPI_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		mx-supply = <&VDD_LPI_MX_LEVEL>;
		mx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 0>;
		reg-names = "cx", "mx";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "crypto_ddr";

		qcom,qmp = <&aoss_qmp>;

		memory-region = <&adsp_mem>;

		/* Inputs from ssc */
		interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>,
					<&adsp_smp2p_in 0 0>,
					<&adsp_smp2p_in 2 0>,
					<&adsp_smp2p_in 1 0>,
					<&adsp_smp2p_in 3 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&adsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";

		status = "ok";

		glink_edge: glink-edge {
			qcom,remote-pid = <2>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "adsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_LPASS
					IPCC_MPROC_SIGNAL_GLINK_QMP
					IRQ_TYPE_EDGE_RISING>;

			label = "adsp";
			qcom,glink-label = "lpass";

			qcom,adsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
				qcom,no-wake-svc = <0x190>;
			};

			qcom,msm_fastrpc_rpmsg {
					compatible = "qcom,msm-fastrpc-rpmsg";
					qcom,glink-channels = "fastrpcglink-apps-dsp";
					qcom,intents = <0x64 64>;
			};

			qcom,pmic_glink_rpmsg {
				qcom,glink-channels = "PMIC_RTR_ADSP_APPS";
			};

			qcom,pmic_glink_log_rpmsg {
				qcom,glink-channels = "PMIC_LOGS_ADSP_APPS";
				qcom,intents = <0x800 5
						0xc00 3
						0x2000 1>;
			};
		};
	};

	cdsp_pas: remoteproc-cdsp@32300000 {
		compatible = "qcom,anorak-cdsp-pas";
		reg = <0x32300000 0x10000>;

		cx-supply = <&VDD_CX_LEVEL>;
		cx-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mxa-supply = <&VDD_MXA_LEVEL>;
		mxa-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		mxc-supply = <&VDD_MXC_LEVEL>;
		mxc-uV-uA = <RPMH_REGULATOR_LEVEL_TURBO 100000>;
		reg-names = "cx","mxa","mxc";

		clocks = <&rpmhcc RPMH_CXO_CLK>;
		clock-names = "xo";

		interconnects = <&nsp_noc MASTER_CDSP_PROC &mc_virt SLAVE_EBI1>,
				<&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		interconnect-names = "rproc_ddr", "crypto_ddr";

		qcom,qmp = <&aoss_qmp>;

		memory-region = <&cdsp_mem>;

		/* Inputs from turing */
		interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>,
					<&cdsp_smp2p_in 0 0>,
					<&cdsp_smp2p_in 2 0>,
					<&cdsp_smp2p_in 1 0>,
					<&cdsp_smp2p_in 3 0>;

		interrupt-names = "wdog",
				"fatal",
				"handover",
				"ready",
				"stop-ack";

		/* Outputs to turing */
		qcom,smem-states = <&cdsp_smp2p_out 0>;
		qcom,smem-state-names = "stop";
		status = "ok";

		glink-edge {
			qcom,remote-pid = <5>;
			transport = "smem";
			mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP
					  IPCC_MPROC_SIGNAL_GLINK_QMP>;
			mbox-names = "cdsp_smem";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_CDSP
				  IPCC_MPROC_SIGNAL_GLINK_QMP
				  IRQ_TYPE_EDGE_RISING>;

			label = "cdsp";
			qcom,glink-label = "cdsp";

			qcom,cdsp_qrtr {
				qcom,glink-channels = "IPCRTR";
				qcom,intents = <0x800  5
						0x2000 3
						0x4400 2>;
			};

			qcom,msm_fastrpc_rpmsg {
				compatible = "qcom,msm-fastrpc-rpmsg";
				qcom,glink-channels = "fastrpcglink-apps-dsp";
				qcom,intents = <0x64 64>;
			};
		};
	};


	llcc_pmu: llcc-pmu@19095000 {
		compatible = "qcom,llcc-pmu-ver2";
		reg = <0x19095000 0x300>;
		reg-names = "lagg-base";
	};

	qcom_pmu: qcom,pmu {
		compatible = "qcom,pmu";
		reg = < 0x17D09300 0x300>;
		reg-names = "pmu-base";
		qcom,pmu-events-tbl =
			< 0x0008 0x3F 0xFF 0x02 >,
			< 0x0011 0x3F 0xFF 0x00 >,
			< 0x0017 0x3F 0xFF 0xFF >,
			< 0x002A 0x3F 0xFF 0xFF >,
			< 0x4005 0x3F 0xFF 0xFF >,
			< 0x1000 0x3F 0xFF 0xFF >;
	};

	ddr_freq_table: ddr-freq-table {
		qcom,freq-tbl =
			<  547200 >,
			<  681600 >,
			<  768000 >,
			< 1555200 >,
			< 1708800 >,
			< 2092800 >,
			< 2736000 >,
			< 3196800 >;
	};

	llcc_freq_table: llcc-freq-table {
		qcom,freq-tbl =
			<  300000 >,
			<  466500 >,
			<  600000 >,
			<  806000 >,
			<  933000 >,
			< 1066000 >;
	};

	ddrqos_freq_table: ddrqos-freq-table {
		qcom,freq-tbl =
		< 0 >,
		< 1 >;
	};

	qcom_dcvs: qcom,dcvs {
		compatible = "qcom,dcvs";
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		qcom_l3_dcvs_hw: l3 {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <2>;
			qcom,bus-width = <32>;
			reg = <0x17d90000 0x4000>, <0x17d90100 0xa0>;
			reg-names = "l3-base", "l3tbl-base";

			l3_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				qcom,shared-offset = <0x0090>;
			};
		};

		qcom_ddr_dcvs_hw: ddr {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <0>;
			qcom,bus-width = <4>;
			qcom,freq-tbl = <&ddr_freq_table>;

			ddr_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&mc_virt MASTER_LLCC
						 &mc_virt SLAVE_EBI1>;
			};

			ddr_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};

		};

		qcom_llcc_dcvs_hw: llcc {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <1>;
			qcom,bus-width = <16>;
			qcom,freq-tbl = <&llcc_freq_table>;

			llcc_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&gem_noc MASTER_APPSS_PROC
						 &gem_noc SLAVE_LLCC>;
			};

			llcc_dcvs_fp: fp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <1>;
				qcom,fp-voter = <&dcvs_fp>;
			};

		};

		qcom_ddrqos_dcvs_hw: ddrqos {
			compatible = "qcom,dcvs-hw";
			qcom,dcvs-hw-type = <3>;
			qcom,bus-width = <1>;
			qcom,freq-tbl = <&ddrqos_freq_table>;

			ddrqos_dcvs_sp: sp {
				compatible = "qcom,dcvs-path";
				qcom,dcvs-path-type = <0>;
				interconnects = <&mc_virt MASTER_LLCC
					 &mc_virt SLAVE_EBI1>;
			};
		};
	};

	qcom_memlat: qcom,memlat {
		compatible = "qcom,memlat";
		qcom,be-stall-ev = <0x4005>;
		ddr {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddr_dcvs_hw>;
			qcom,sampling-path = <&ddr_dcvs_fp>;
			qcom,miss-ev = <0x1000>;

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,sampling-enabled;
				qcom,cpufreq-memfreq-tbl =
					<  960000  547000 >,
					< 1228800  768000 >,
					< 1651200 1555000 >,
					< 1920000 1708000 >,
					< 2208000 2092000 >,
					< 2361600 3196000 >;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,sampling-enabled;
				qcom,cpufreq-memfreq-tbl =
					<  960000  547000 >,
					< 1228800  768000 >,
					< 1651200 1555000 >,
					< 1920000 1708000 >,
					< 2208000 2092000 >,
					< 2361600 3196000 >;
				};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,sampling-enabled;
				qcom,compute-mon;
				qcom,cpufreq-memfreq-tbl =
					< 1228800  547000 >,
					< 1516800  768000 >,
					< 1651200 1555000 >,
					< 1920000 1708000 >,
					< 2208000 2092000 >,
					< 2361600 3196000 >;
			};

			prime-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,sampling-enabled;
				qcom,compute-mon;
				qcom,cpufreq-memfreq-tbl =
					< 1228800  547000 >,
					< 1516800  768000 >,
					< 1651200 1555000 >,
					< 1920000 1708000 >,
					< 2208000 2092000 >,
					< 2361600 3196000 >;
			};
		};

		llcc {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_llcc_dcvs_hw>;
			qcom,sampling-path = <&llcc_dcvs_fp>;
			qcom,miss-ev = <0x2A>;

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					<  691200  300000 >,
					<  960000  466500 >,
					< 1228800  600000 >,
					< 1651200  806000 >,
					< 2208000  933000 >,
					< 2361600 1066000 >;
				qcom,sampling-enabled;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,cpufreq-memfreq-tbl =
					<  691200  300000 >,
					<  960000  466500 >,
					< 1228800  600000 >,
					< 1651200  806000 >,
					< 2208000  933000 >,
					< 2361600 1066000 >;
				qcom,sampling-enabled;
			};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					< 1920000  300000 >,
					< 2361600  600000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};

			prime-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,cpufreq-memfreq-tbl =
					< 1920000  300000 >,
					< 2361600  600000 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		l3 {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_l3_dcvs_hw>;
			qcom,sampling-path = <&l3_dcvs_sp>;
			qcom,miss-ev = <0x17>;

			gold {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					<  307200  307200 >,
					<  691200  422400 >,
					<  960000  556800 >,
					< 1094400  691200 >,
					< 1228800  825600 >,
					< 1382400  940800 >,
					< 1516800 1075200 >,
					< 1651200 1209600 >,
					< 1920000 1305600 >,
					< 2054400 1401600 >,
					< 2361600 1516800 >;
				qcom,sampling-enabled;
			};

			prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,cpufreq-memfreq-tbl =
					<  307200  307200 >,
					<  691200  422400 >,
					<  960000  556800 >,
					< 1094400  691200 >,
					< 1228800  825600 >,
					< 1382400  940800 >,
					< 1516800 1075200 >,
					< 1651200 1209600 >,
					< 1920000 1305600 >,
					< 2054400 1401600 >,
					< 2361600 1516800 >;
				qcom,sampling-enabled;
			};

			gold-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU0 &CPU1>;
				qcom,cpufreq-memfreq-tbl =
					< 1920000  307200 >,
					< 2361600 1305600 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};

			prime-compute {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,cpufreq-memfreq-tbl =
					< 1920000  307200 >,
					< 2361600 1305600 >;
				qcom,sampling-enabled;
				qcom,compute-mon;
			};
		};

		ddrqos {
			compatible = "qcom,memlat-grp";
			qcom,target-dev = <&qcom_ddrqos_dcvs_hw>;
			qcom,sampling-path = <&ddrqos_dcvs_sp>;
			qcom,miss-ev = <0x1000>;

			ddrqos_prime_lat: prime {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,cpufreq-memfreq-tbl =
					<  300000 0 >,
					< 2361600 1 >;
				qcom,sampling-enabled;
			};

			ddrqos_prime_latfloor: prime-latfloor {
				compatible = "qcom,memlat-mon";
				qcom,cpulist = <&CPU2 &CPU3 &CPU4 &CPU5>;
				qcom,cpufreq-memfreq-tbl =
					< 1920000 0 >,
					< 2361600 1 >;
				qcom,sampling-enabled;
			};
		};
	};

	bwmon_llcc: qcom,bwmon-llcc@190b6400 {
		compatible = "qcom,bwmon4";
		reg = <0x190b6400 0x300>, <0x190b6300 0x200>;
		reg-names = "base", "global_base";
		interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>;
		qcom,mport = <0>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_llcc_dcvs_hw>;
	};

	bwmon_ddr: qcom,bwmon-ddr@19091000 {
		compatible = "qcom,bwmon5";
		reg = <0x19091000 0x1000>;
		reg-names = "base";
		interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
		qcom,hw-timer-hz = <19200000>;
		qcom,count-unit = <0x10000>;
		qcom,target-dev = <&qcom_ddr_dcvs_hw>;
	};

	bwprof: qcom,bwprof-ddr@19090000 {
		compatible = "qcom,bwprof";
		#address-cells = <1>;
		#size-cells = <1>;
		qcom,bus-width = <16>;
		ranges;
		reg = <0x190BA050 0x10>;
		reg-names = "mem-freq";

		bwprof_0: qcom,bwprof0@19092000 {
			compatible = "qcom,bwprof-mon";
			reg = <0x19092000 0x1000>;
			reg-names = "base";
			client = "total";
		};

		bwprof_1: qcom,bwprof1@19093000 {
			compatible = "qcom,bwprof-mon";
			reg = <0x19093000 0x1000>;
			reg-names = "base";
			client = "cpu";
		};

		bwprof_2: qcom,bwprof2@19094000 {
			compatible = "qcom,bwprof-mon";
			reg = <0x19094000 0x1000>;
			reg-names = "base";
			client = "gpu";
		};

	};

	rimps: qcom,rimps@17400000 {
		#address-cells = <2>;
		#size-cells = <2>;
		compatible = "qcom,rimps";
		reg =   <0x17400000 0x10>,
			<0x17d90000 0x2000>;
		#mbox-cells = <1>;
		interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
	};

	scmi: qcom,scmi {
		#address-cells = <1>;
		#size-cells = <0>;
		compatible = "arm,scmi";
		mboxes = <&rimps 0>;
		mbox-names = "tx";
		shmem = <&cpu_scp_lpri>;

		scmi_plh: protocol@81 {
			reg = <0x81>;
			#clock-cells = <1>;
		};

		scmi_pmu: protocol@86 {
			reg = <0x86>;
			#clock-cells = <1>;
		};

	};

	rimps_log: qcom,rimps_log@17d09c00 {
		compatible = "qcom,rimps-log";
		reg = <0x17d09c00 0x200>, <0x17d09e00 0x200>;
		mboxes = <&rimps 1>;
	};

	ipcc_mproc: qcom,ipcc@ed18000 {
		compatible = "qcom,ipcc";
		reg = <0x408000 0x1000>;
		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	ipcc_compute_l0: qcom,ipcc_compute_l0@448000 {
		compatible = "qcom,ipcc";
		reg = <0x448000 0x1000>;
		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <3>;
		#mbox-cells = <2>;
	};

	ipclite {
		compatible = "qcom,ipclite";
		memory-region = <&global_sync_mem>;
		hwlocks = <&tcsr_mutex 11>;
		#address-cells = <1>;
		#size-cells = <1>;
		ranges;

		ipclite_apss: apss {
			qcom,remote-pid = <0>;
			label = "apss";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
					interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_BROADCAST
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_BROADCAST
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_APSS
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};
		};

		ipclite_cdsp: cdsp {
			qcom,remote-pid = <5>;
			label = "cdsp";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CDSP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};
		};

		ipclite_cvp: cvp {
			qcom,remote-pid = <6>;
			label = "cvp";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_CVP
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};
		};

		ipclite_vpu: vpu {
			qcom,remote-pid = <8>;
			label = "vpu";
			global_atomic = <1>;

			ipclite_signal_0 {
				index = <0>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MSG
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_1 {
				index = <1>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_MEM_INIT
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_2 {
				index = <2>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_VERSION
					IRQ_TYPE_EDGE_RISING>;
			};

			ipclite_signal_3 {
				index = <3>;
				mboxes = <&ipcc_compute_l0 IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST>;
				interrupt-parent = <&ipcc_compute_l0>;
				interrupts = <IPCC_CLIENT_VPU
					IPCC_COMPUTE_L0_SIGNAL_IPCLITE_TEST
					IRQ_TYPE_EDGE_RISING>;
			};
		};
	};

	aoss_qmp: power-controller@c300000 {
		compatible = "qcom,anorak-aoss-qmp";
		reg = <0xc300000 0x400>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_AOP
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_AOP
		IPCC_MPROC_SIGNAL_GLINK_QMP>;

		#power-domain-cells = <1>;
		#clock-cells = <0>;
	};

	qmp_aop: qcom,qmp-aop {
		compatible = "qcom,qmp-mbox";
		qcom,qmp = <&aoss_qmp>;
		label = "aop";
		#mbox-cells = <1>;
	};

	qmp_tme: qcom,qmp-tme {
		compatible = "qcom,qmp-mbox";
		qcom,remote-pid = <14>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP>;
		mbox-names = "tme_qmp";
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_TME
				IPCC_MPROC_SIGNAL_GLINK_QMP
				IRQ_TYPE_EDGE_RISING>;

		label = "tme";
		qcom,early-boot;
		priority = <0>;
		mbox-desc-offset = <0x0>;
		#mbox-cells = <1>;
	};

	qcom,tmecom-qmp-client {
		compatible = "qcom,tmecom-qmp-client";
		mboxes = <&qmp_tme 0>;
		mbox-names = "tmecom";
		label = "tmecom";
		depends-on-supply = <&qmp_tme>;
	};

	qcom,glinkpkt {
		compatible = "qcom,glinkpkt";

		qcom,glinkpkt-apr-apps2 {
			qcom,glinkpkt-edge = "adsp";
			qcom,glinkpkt-ch-name = "apr_apps2";
			qcom,glinkpkt-dev-name = "apr_apps2";
		};
	};

	qcom,glink {
		compatible = "qcom,glink";
	};

	tcsr: syscon@1fc0000 {
		compatible = "syscon";
		reg = <0x1fc0000 0x30000>;
	};

	tcsr_mutex_block: syscon@1f40000 {
		compatible = "syscon";
		reg = <0x1f40000 0x20000>;
	};

	tcsr_mutex: hwlock {
		compatible = "qcom,tcsr-mutex";
		syscon = <&tcsr_mutex_block 0 0x1000>;
		#hwlock-cells = <1>;
		};

	qcom_cedev: qcedev@1de0000 {
		compatible = "qcom,qcedev";
		reg = <0x1de0000 0x20000>,
			<0x1dc4000 0x24000>;
		reg-names = "crypto-base","crypto-bam-base";
		interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
		qcom,bam-pipe-pair = <2>;
		qcom,offload-ops-support;
		qcom,bam-pipe-offload-cpb-hlos = <1>;
		qcom,bam-pipe-offload-hlos-cpb = <3>;
		qcom,ce-hw-instance = <0>;
		qcom,ce-device = <0>;
		qcom,ce-hw-shared;
		qcom,bam-ee = <0>;
		qcom,smmu-s1-enable;
		qcom,no-clock-support;
		interconnect-names = "data_path";
		interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>;
		iommus = <&apps_smmu 0x0480 0x0>,
			<&apps_smmu 0x0481 0x0>;
		qcom,iommu-dma = "atomic";
		dma-coherent;

		qcom_cedev_ns_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "ns_context";
			iommus = <&apps_smmu 0x0481 0x0>;
			dma-coherent;
		};

		qcom_cedev_s_cb {
			compatible = "qcom,qcedev,context-bank";
			label = "secure_context";
			iommus = <&apps_smmu 0x0483 0x0>;
			qcom,iommu-vmid = <0x9>;
			qcom,secure-context-bank;
			dma-coherent;
		};
	};

	qcom_rng: qrng@10c3000 {
		compatible = "qcom,msm-rng";
		reg = <0x10c3000 0x1000>;
		qcom,no-qrng-config;
		qcom,no-clock-support;
	};

	smem: qcom,smem {
		compatible = "qcom,smem";
		memory-region = <&smem_mem>;
		hwlocks = <&tcsr_mutex 3>;
	};

	qcom,chd {
		compatible = "qcom,core-hang-detect";
		label = "core";
		qcom,threshold-arr = <0x17800058 0x17810058 0x17820058 0x17830058 0x17840058 0x17850058>;
		qcom,config-arr =<0x17800060 0x17810060 0x17820060 0x17830060 0x17840060 0x17850060>;
	};

	qcom,msm-rtb {
		compatible = "qcom,msm-rtb";
		qcom,rtb-size = <0x100000>;
	};

	clk_virt: interconnect@0 {
		compatible = "qcom,anorak-clk_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	mc_virt: interconnect@1 {
		compatible = "qcom,anorak-mc_virt";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp0", "disp1";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp0_bcm_voter>, <&disp1_bcm_voter>;
	};

	config_noc: interconnect@1500000 {
		reg = <0x1500000 0x13080>;
		compatible = "qcom,anorak-config_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	system_noc: interconnect@1680000 {
		reg = <0x01680000 0x13080>;
		compatible = "qcom,anorak-system_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	pcie_noc: interconnect@16c0000 {
		reg = <0x16C0000 0xC080>;
		compatible = "qcom,anorak-pcie_anoc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>,
			<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>,
			<&gcc GCC_AGGRE_NOC_PCIE_SF_AXI_CLK>;
	};

	aggre1_noc: interconnect@16e0000 {
		reg = <0x16E0000 0x9080>;
		compatible = "qcom,anorak-aggre1_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
	};

	aggre2_noc: interconnect@1700000 {
		reg = <0x1700000 0x15080>;
		compatible = "qcom,anorak-aggre2_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
		clocks = <&rpmhcc RPMH_IPA_CLK>;
	};

	mmss_noc: interconnect@1740000 {
		reg = <0x01740000 0x1C100>;
		compatible = "qcom,anorak-mmss_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp0", "disp1";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp0_bcm_voter>, <&disp1_bcm_voter>;
	};

	gem_noc: interconnect@19100000 {
		reg = <0x19100000 0xA9080>;
		compatible = "qcom,anorak-gem_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos", "disp0", "disp1";
		qcom,bcm-voters = <&apps_bcm_voter>, <&disp0_bcm_voter>, <&disp1_bcm_voter>;
	};

	nsp_noc: interconnect@320C0000 {
		reg = <0x320C0000 0x10000>;
		compatible = "qcom,anorak-nsp_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	lpass_ag_noc: interconnect@3c40000 {
		reg = <0x3c40000 0x17200>;
		compatible = "qcom,anorak-lpass_ag_noc";
		#interconnect-cells = <1>;
		qcom,bcm-voter-names = "hlos";
		qcom,bcm-voters = <&apps_bcm_voter>;
	};

	qcom,qsee_ipc_irq_bridge {
		compatible = "qcom,qsee-ipc-irq-bridge";
		qcom,qsee-ipc-irq-spss {
			qcom,dev-name = "qsee_ipc_irq_spss";
			interrupt-parent = <&ipcc_mproc>;
			interrupts = <IPCC_CLIENT_SPSS
					IPCC_MPROC_SIGNAL_TZ
					IRQ_TYPE_EDGE_RISING>;
			label = "spss";
		};
	};

	qcom,secure-buffer {
		compatible = "qcom,secure-buffer";
		qcom,vmid-cp-camera-preview-ro;
	};

	qcom,msm-cdsp-loader {
		compatible = "qcom,cdsp-loader";
		qcom,proc-img-to-load = "cdsp";
		qcom,rproc-handle = <&cdsp_pas>;
	};

	qcom,msm-adsprpc-mem {
		compatible = "qcom,msm-adsprpc-mem-region";
		memory-region = <&adsp_mem_heap>;
		restrict-access;
	};

	qcom,sps {
		compatible = "qcom,msm-sps-4k";
		qcom,pipe-attr-ee;
	};

	msm_fastrpc: qcom,msm_fastrpc {
		compatible = "qcom,msm-fastrpc-compute";
		qcom,adsp-remoteheap-vmid = <22 37>;
		qcom,fastrpc-adsp-audio-pdr;
		qcom,fastrpc-adsp-sensors-pdr;
		qcom,rpc-latency-us = <235>;
		qcom,fastrpc-gids = <2908>;
		qcom,qos-cores = <2>; /* its a gold+ cluster */

		qcom,msm_fastrpc_compute_cb1 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0961 0x0420>,
					 <&apps_smmu 0x2021 0x0560>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb2 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0962 0x0400>,
					 <&apps_smmu 0x2022 0x0460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb3 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0963 0x0C60>,
					 <&apps_smmu 0x2023 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb4 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0964 0x0560>,
					 <&apps_smmu 0x2024 0x2420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb5 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0965 0x0540>,
					 <&apps_smmu 0x2025 0x0520>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb6 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0966 0x0440>,
					 <&apps_smmu 0x2026 0x2520>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb7 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0967 0x0520>,
					 <&apps_smmu 0x2027 0x0560>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb8 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x0968 0x0440>,
					 <&apps_smmu 0x2028 0x0420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb9 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			qcom,secure-context-bank;
			iommus = <&apps_smmu 0x0969 0x0560>,
					 <&apps_smmu 0x2029 0x2520>;
			qcom,iommu-dma-addr-pool = <0x60000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			qcom,iommu-vmid = <0xA>;	/* VMID_CP_PIXEL */
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb10 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x2803 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb11 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x2804 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb12 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "adsprpc-smd";
			iommus = <&apps_smmu 0x2805 0x0>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
			shared-cb = <5>;
		};

		qcom,msm_fastrpc_compute_cb13 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x096B 0x0400>,
					 <&apps_smmu 0x202B 0x2420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb14 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x096C 0x0C60>,
					 <&apps_smmu 0x202C 0x0460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb15 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x096D 0x0D00>,
					 <&apps_smmu 0x202D 0x2420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb16 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x096E 0x0560>,
					 <&apps_smmu 0x202E 0x0460>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};

		qcom,msm_fastrpc_compute_cb17 {
			compatible = "qcom,msm-fastrpc-compute-cb";
			label = "cdsprpc-smd";
			iommus = <&apps_smmu 0x096F 0x0540>,
					 <&apps_smmu 0x202F 0x2420>;
			qcom,iommu-dma-addr-pool = <0x80000000 0x78000000>;
			qcom,iommu-faults = "stall-disable", "HUPCF";
			dma-coherent;
		};
	};

	qcom,mem-buf-msgq {
		compatible = "qcom,mem-buf-msgq";
	};

	qcom,mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "supplier";
		qcom,vmid = <3>;
	};

	qcom,smp2p-adsp {
		compatible = "qcom,smp2p";
		qcom,smem = <443>, <429>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_LPASS IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_LPASS
			  IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <2>;

		adsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		adsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		sleepstate_smp2p_out: sleepstate-out {
			qcom,entry-name = "sleepstate";
			#qcom,smem-state-cells = <1>;
		};

		sleepstate_smp2p_in: qcom,sleepstate-in {
			qcom,entry-name = "sleepstate_see";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg2_out: qcom,smp2p-rdbg2-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg2_in: qcom,smp2p-rdbg2-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p-cdsp {
		compatible = "qcom,smp2p";
		qcom,smem = <94>, <432>;
		interrupt-parent = <&ipcc_mproc>;
		interrupts = <IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P
			      IRQ_TYPE_EDGE_RISING>;
		mboxes = <&ipcc_mproc IPCC_CLIENT_CDSP IPCC_MPROC_SIGNAL_SMP2P>;
		qcom,local-pid = <0>;
		qcom,remote-pid = <5>;

		cdsp_smp2p_out: master-kernel {
			qcom,entry-name = "master-kernel";
			#qcom,smem-state-cells = <1>;
		};

		cdsp_smp2p_in: slave-kernel {
			qcom,entry-name = "slave-kernel";
			interrupt-controller;
			#interrupt-cells = <2>;
		};

		smp2p_rdbg5_out: qcom,smp2p-rdbg5-out {
			qcom,entry-name = "rdbg";
			#qcom,smem-state-cells = <1>;
		};

		smp2p_rdbg5_in: qcom,smp2p-rdbg5-in {
			qcom,entry-name = "rdbg";
			interrupt-controller;
			#interrupt-cells = <2>;
		};
	};

	qcom,smp2p_sleepstate {
		compatible = "qcom,smp2p-sleepstate";
		qcom,smem-states = <&sleepstate_smp2p_out 0>;
		interrupt-parent = <&sleepstate_smp2p_in>;
		interrupts = <0 0>;
		interrupt-names = "smp2p-sleepstate-in";
	};

	mhi_qrtr_cnss {
		compatible = "qcom,qrtr-mhi";
		qcom,dev-id = <0x1103>;
		qcom,net-id = <0>;
		qcom,low-latency;
	};

	sdhc2_opp_table: sdhc2-opp-table {
		compatible = "operating-points-v2";

		opp-100000000 {
			opp-hz = /bits/ 64 <100000000>;
			opp-peak-kBps = <1600000 280000>;
			opp-avg-kBps = <50000 0>;
		};

		opp-202000000 {
			opp-hz = /bits/ 64 <202000000>;
			opp-peak-kBps = <5600000 1500000>;
			opp-avg-kBps = <104000 0>;
		};
	};

	sdhc_2: sdhci@8804000 {
		status = "disabled";

		compatible = "qcom,sdhci-msm-v5";
		reg = <0x08804000 0x1000>;
		reg-names = "hc";

		interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>,
				<GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "hc_irq", "pwr_irq";

		bus-width = <4>;
		no-sdio;
		no-mmc;

		clocks = <&gcc GCC_SDCC2_AHB_CLK>,
			<&gcc GCC_SDCC2_APPS_CLK>;
		clock-names = "iface", "core";

		/* DLL HSR settings. Refer go/hsr - <Target> DLL settings */
		qcom,dll-hsr-list = <0x0007642C 0x0 0x10
					0x2C010800 0x80040868>;

		iommus = <&apps_smmu 0x420 0x0>;
		dma-coherent;
		qcom,iommu-dma = "fastmap";

		interconnects = <&aggre2_noc MASTER_SDCC_2 &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_SDCC_2>;
		interconnect-names = "sdhc-ddr","cpu-sdhc";
		operating-points-v2 = <&sdhc2_opp_table>;

		qos0 {
			mask = <0xf0>;
			vote = <44>;
		};

		qos1 {
			mask = <0x03>;
			vote = <44>;
		};
	};

	ufsphy_mem: ufsphy_mem@1d87000 {
		reg = <0x1d87000 0xe10>;
		reg-names = "phy_mem";
		#phy-cells = <0>;

		lanes-per-direction = <2>;
		clock-names = "ref_clk_src",
			"ref_aux_clk",
			"qref_clk",
			"rx_sym0_mux_clk", "rx_sym1_mux_clk", "tx_sym0_mux_clk",
			"rx_sym0_phy_clk", "rx_sym1_phy_clk", "tx_sym0_phy_clk";
		clocks = <&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
			<&gcc GCC_UFS_0_CLKREF_EN>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK_SRC>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK_SRC>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK_SRC>,
			<&ufs_phy_rx_symbol_0_clk>,
			<&ufs_phy_rx_symbol_1_clk>,
			<&ufs_phy_tx_symbol_0_clk>;

		resets = <&ufshc_mem 0>;
		status = "disabled";
	};

	ufshc_mem: ufshc@1d84000 {
		compatible = "qcom,ufshc";
		reg = <0x1d84000 0x3000>,
			<0x1d88000 0x8000>,
			<0x1d90000 0x9000>;
		reg-names = "ufs_mem", "ufs_ice", "ufs_ice_hwkm";
		interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
		phys = <&ufsphy_mem>;
		phy-names = "ufsphy";
		#reset-cells = <1>;
		spm-level = <5>;
		lanes-per-direction = <2>;
		dev-ref-clk-freq = <0>; /* 19.2 MHz */
		clock-names =
			"core_clk",
			"bus_aggr_clk",
			"iface_clk",
			"core_clk_unipro",
			"core_clk_ice",
			"ref_clk",
			"tx_lane0_sync_clk",
			"rx_lane0_sync_clk",
			"rx_lane1_sync_clk";
		clocks =
			<&gcc GCC_UFS_PHY_AXI_CLK>,
			<&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
			<&gcc GCC_UFS_PHY_AHB_CLK>,
			<&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
			<&gcc GCC_UFS_PHY_ICE_CORE_CLK>,
			<&rpmhcc RPMH_CXO_CLK>,
			<&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
			<&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
		freq-table-hz =
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<75000000 300000000>,
			<75000000 300000000>,
			<0 0>,
			<0 0>,
			<0 0>,
			<0 0>;

		interconnects = <&aggre1_noc MASTER_UFS_MEM &mc_virt SLAVE_EBI1>,
		      <&gem_noc MASTER_APPSS_PROC &config_noc SLAVE_UFS_MEM_CFG>;
		interconnect-names = "ufs-ddr", "cpu-ufs";

		qcom,ufs-bus-bw,name = "ufshc_mem";
		qcom,ufs-bus-bw,num-cases = <26>;
		qcom,ufs-bus-bw,num-paths = <2>;
		qcom,ufs-bus-bw,vectors-KBps =
		/*
		 * During HS G3 UFS runs at nominal voltage corner, vote
		 * higher bandwidth to push other buses in the data path
		 * to run at nominal to achieve max throughput.
		 * 4GBps pushes BIMC to run at nominal.
		 * 200MBps pushes CNOC to run at nominal.
		 * Vote for half of this bandwidth for HS G3 1-lane.
		 * For max bandwidth, vote high enough to push the buses
		 * to run in turbo voltage corner.
		 */
		<0 0>, <0 0>,          /* No vote */
		<922 0>, <1000 0>,     /* PWM G1 */
		<1844 0>, <1000 0>,    /* PWM G2 */
		<3688 0>, <1000 0>,    /* PWM G3 */
		<7376 0>, <1000 0>,    /* PWM G4 */
		<1844 0>, <1000 0>,    /* PWM G1 L2 */
		<3688 0>, <1000 0>,    /* PWM G2 L2 */
		<7376 0>, <1000 0>,    /* PWM G3 L2 */
		<14752 0>, <1000 0>,   /* PWM G4 L2 */
		<127796 0>, <1000 0>,  /* HS G1 RA */
		<255591 0>, <1000 0>,  /* HS G2 RA */
		<1492582 0>, <102400 0>,  /* HS G3 RA */
		<2915200 0>, <204800 0>,  /* HS G4 RA */
		<255591 0>, <1000 0>,  /* HS G1 RA L2 */
		<511181 0>, <1000 0>,  /* HS G2 RA L2 */
		<1492582 0>, <204800 0>, /* HS G3 RA L2 */
		<2915200 0>, <409600 0>, /* HS G4 RA L2 */
		<149422 0>, <1000 0>,  /* HS G1 RB */
		<298189 0>, <1000 0>,  /* HS G2 RB */
		<1492582 0>, <102400 0>,  /* HS G3 RB */
		<2915200 0>, <204800 0>,  /* HS G4 RB */
		<298189 0>, <1000 0>,  /* HS G1 RB L2 */
		<596378 0>, <1000 0>,  /* HS G2 RB L2 */
		/* As UFS working in HS G3 RB L2 mode, aggregated
		 * bandwidth (AB) should take care of providing
		 * optimum throughput requested. However, as tested,
		 * in order to scale up CNOC clock, instantaneous
		 * bindwidth (IB) needs to be given a proper value too.
		 */
		<1492582 0>, <204800 409600>, /* HS G3 RB L2 KBPs */
		<2915200 0>, <409600 409600>, /* HS G4 RB L2 */
		<7643136 0>, <307200 0>; /* Max. bandwidth */

		qcom,bus-vector-names = "MIN",
		"PWM_G1_L1", "PWM_G2_L1", "PWM_G3_L1", "PWM_G4_L1",
		"PWM_G1_L2", "PWM_G2_L2", "PWM_G3_L2", "PWM_G4_L2",
		"HS_RA_G1_L1", "HS_RA_G2_L1", "HS_RA_G3_L1", "HS_RA_G4_L1",
		"HS_RA_G1_L2", "HS_RA_G2_L2", "HS_RA_G3_L2", "HS_RA_G4_L2",
		"HS_RB_G1_L1", "HS_RB_G2_L1", "HS_RB_G3_L1", "HS_RB_G4_L1",
		"HS_RB_G1_L2", "HS_RB_G2_L2", "HS_RB_G3_L2", "HS_RB_G4_L2",
		"MAX";

		iommus = <&apps_smmu 0x60 0x0>;
		qcom,iommu-dma = "fastmap";
		dma-coherent;

		reset-gpios = <&tlmm 224 GPIO_ACTIVE_LOW>;
		resets = <&gcc GCC_UFS_PHY_BCR>;
		reset-names = "rst";

		status = "disabled";

		qos0 {
			mask = <0x30>;
			vote = <44>;
			perf;
		};

		qos1 {
			mask = <0x0f>;
			vote = <44>;
		};
	};

	vendor_hooks: qcom,cpu-vendor-hooks {
		compatible = "qcom,cpu-vendor-hooks";
	};

	logbuf: qcom,logbuf-vendor-hooks {
		compatible = "qcom,logbuf-vendor-hooks";
	};

	qfprom: qfprom@221c8000 {
		compatible = "qcom,qfprom";
		reg = <0x221c8000 0x1000>;
		#address-cells = <1>;
		#size-cells = <1>;
		read-only;
		ranges;

		feat_conf10: feat_conf10@128 {
			reg = <0x128 0x4>;
		};

		feat_conf11: feat_conf11@12c {
			reg = <0x12c 0x4>;
		};

		gpu_speed_bin: gpu_speed_bin@119 {
			reg = <0x119 0x2>;
			bits = <7 8>;
		};
	};

	qfprom_sys: qfprom@0 {
		compatible = "qcom,qfprom-sys";

		nvmem-cells = <&feat_conf10>,
				<&feat_conf11>,
				<&gpu_speed_bin>;
		nvmem-cell-names = "feat_conf10",
				"feat_conf11",
				"gpu_speed_bin";
	};

	eud: qcom,msm-eud@88e0000 {
		compatible = "qcom,msm-eud";
		interrupt-names = "eud_irq";
		interrupt-parent = <&pdc>;
		interrupts = <11 IRQ_TYPE_LEVEL_HIGH>;
		reg = <0x088e0000 0x2000>,
			<0x088e2000 0x1000>;
		reg-names = "eud_base", "eud_mode_mgr2";
		qcom,secure-eud-en;
		status = "ok";
	};

	qcom_tzlog: tz-log@146AA720 {
		compatible = "qcom,tz-log";
		reg = <0x146AA720 0x3000>;
		qcom,hyplog-enabled;
		hyplog-address-offset = <0x410>;
		hyplog-size-offset = <0x414>;
	};

	qcom_qseecom: qseecom@c1700000 {
		compatible = "qcom,qseecom";
		memory-region = <&qseecom_mem>;
		qseecom_mem = <&qseecom_mem>;
		qseecom_ta_mem = <&qseecom_ta_mem>;
		user_contig_mem = <&user_contig_mem>;
		qcom,hlos-num-ce-hw-instances = <1>;
		qcom,hlos-ce-hw-instance = <0>;
		qcom,qsee-ce-hw-instance = <0>;
		qcom,disk-encrypt-pipe-pair = <2>;
		qcom,no-clock-support;
		qcom,appsbl-qseecom-support;
		qcom,commonlib64-loaded-by-uefi;
		qcom,qsee-reentrancy-support = <2>;
	};

	thermal_zones: thermal-zones {
	};

	spmi_bus: spmi0_bus: qcom,spmi@c42d000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc42d000 0x4000>,
		      <0xc400000 0x3000>,
		      <0xc500000 0x400000>,
		      <0xc440000 0x80000>,
		      <0xc4c0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <0>;
	};

	spmi1_bus: qcom,spmi@c432000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc432000 0x4000>,
		      <0xc400000 0x3000>,
		      <0xc500000 0x400000>,
		      <0xc440000 0x80000>,
		      <0xc4d0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-names = "periph_irq";
		interrupt-controller;
		#interrupt-cells = <4>;
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <1>;
		depends-on-supply = <&spmi0_bus>;
	};

	spmi0_debug_bus: qcom,spmi-debug@10b14000 {
		compatible = "qcom,spmi-pmic-arb-debug";
		reg = <0x10b14000 0x60>, <0x221c8784 0x4>;
		reg-names = "core", "fuse";
		clocks = <&aoss_qmp>;
		clock-names = "core_clk";
		qcom,fuse-enable-bit = <18>;
		#address-cells = <2>;
		#size-cells = <0>;
		depends-on-supply = <&spmi1_bus>;
		depends-on2-supply = <&smb1394_glink_debug>;

		qcom,pmk8550-debug@0 {
			compatible = "qcom,spmi-pmic";
			reg = <0 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pmxr2230-debug@1 {
			compatible = "qcom,spmi-pmic";
			reg = <1 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8550vs-debug@2 {
			compatible = "qcom,spmi-pmic";
			reg = <2 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8550vs-debug@3 {
			compatible = "qcom,spmi-pmic";
			reg = <3 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8550ve-debug@5 {
			compatible = "qcom,spmi-pmic";
			reg = <5 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8550b-debug@7 {
			compatible = "qcom,spmi-pmic";
			reg = <7 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pmg1110-debug@a {
			compatible = "qcom,spmi-pmic";
			reg = <10 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8010-debug@c {
			compatible = "qcom,spmi-pmic";
			reg = <12 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};

		qcom,pm8010-debug@d {
			compatible = "qcom,spmi-pmic";
			reg = <13 SPMI_USID>;
			#address-cells = <2>;
			#size-cells = <0>;
			qcom,can-sleep;
		};
	};

	qcom,pmic_glink {
		compatible = "qcom,pmic-glink";
		qcom,pmic-glink-channel = "PMIC_RTR_ADSP_APPS";
		qcom,subsys-name = "lpass";
		qcom,protection-domain = "tms/servreg", "msm/adsp/charger_pd";
		depends-on-supply = <&ipcc_mproc>;

		battery_charger: qcom,battery_charger {
			compatible = "qcom,battery-charger";
		};

		ucsi: qcom,ucsi {
			compatible = "qcom,ucsi-glink";
			connector {
				port {
					usb_port0_connector: endpoint {
						remote-endpoint = <&usb_port0>;
					};
				};
			};
		};

		altmode: qcom,altmode {
			compatible = "qcom,altmode-glink";
			#altmode-cells = <1>;
		};
	};

	qcom,pmic_glink_log {
		compatible = "qcom,pmic-glink";
		qcom,pmic-glink-channel = "PMIC_LOGS_ADSP_APPS";

		qcom,battery_debug {
			compatible = "qcom,battery-debug";
		};

		qcom,charger_ulog_glink {
			compatible = "qcom,charger-ulog-glink";
		};

		qcom,spmi_glink_debug {
			compatible = "qcom,spmi-glink-debug";
			#address-cells = <1>;
			#size-cells = <0>;
			depends-on-supply = <&spmi1_bus>;

			/* Primary SPMI bus */
			spmi@0 {
				reg = <0>;
				#address-cells = <2>;
				#size-cells = <0>;

				qcom,pm8550b-debug@7 {
					compatible = "qcom,spmi-pmic";
					reg = <7 SPMI_USID>;
					qcom,can-sleep;
				};
			};

			/* Secondary SPMI bus */
			spmi@1 {
				reg = <1>;
				#address-cells = <2>;
				#size-cells = <0>;

				smb1394_glink_debug: qcom,smb1394-debug@9 {
					compatible = "qcom,spmi-pmic";
					reg = <9 SPMI_USID>;
					qcom,can-sleep;
				};

				qcom,smb1394-debug@b {
					compatible = "qcom,spmi-pmic";
					reg = <11 SPMI_USID>;
					qcom,can-sleep;
				};

				qcom,smb1398-debug@d {
					compatible = "qcom,spmi-pmic";
					reg = <13 SPMI_USID>;
					qcom,can-sleep;
				};
			};
		};
	};
	msm_sdexpress: qcom,msm-sdexpress {
		compatible = "qcom,msm-sdexpress";
		qcom,pcie-nvme-instance = <2>;

		pinctrl-names = "default", "sleep";
		pinctrl-0 = <&pcie2_clkreq_default>;
		pinctrl-1 = <&pcie2_clkreq_sleep>;

		status = "disabled";
	};
};

#include "anorak-qupv3.dtsi"
#include "diwali-gdsc.dtsi"

&qupv3_se6_2uart {
	status = "ok";
};

&qupv3_se5_4uart {
	status = "ok";
};

&cam_cc_bps_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf0004 0x4>;
	status = "ok";
};

&cam_cc_ife_0_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf1004 0x4>;
	status = "ok";
};

&cam_cc_ife_1_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf2004 0x4>;
	status = "ok";
};

&cam_cc_ipe_0_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf03b8 0x4>;
	status = "ok";
};

&cam_cc_titan_top_gdsc {
	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	reg = <0xadf4138 0x4>;
	status = "ok";
};

&disp0_cc_mdss_core_gdsc {
	parent-supply = <&VDD_MM_LEVEL>;
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&disp0_cc_mdss_core_int2_gdsc {
	parent-supply = <&VDD_MM_LEVEL>;
	clocks = <&gcc GCC_DISP_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&disp1_cc_mdss_core_gdsc {
	parent-supply = <&VDD_MM_LEVEL>;
	clocks = <&gcc GCC_DISP1_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&disp1_cc_mdss_core_int2_gdsc {
	parent-supply = <&VDD_MM_LEVEL>;
	clocks = <&gcc GCC_DISP1_AHB_CLK>;
	clock-names = "ahb_clk";
	status = "ok";
};

&gcc_pcie_0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status="ok";
};

&gcc_pcie_1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	reg = <0x1ad004 0x4>;
	qcom,support-hw-trigger;
	status="ok";
};

&gcc_pcie_2_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status="ok";
};

&gcc_ufs_phy_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gcc_usb30_prim_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf2_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf3_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf4_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_hf5_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_mmnoc_mmu_tbu_sf1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu0_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&hlos1_vote_turing_mmu_tbu1_gdsc {
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_cc_cx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_CX_LEVEL>;
	status = "ok";
};

&gpu_cc_gx_gdsc {
	clocks = <&gcc GCC_GPU_CFG_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_GFX_MXC_VOTER_LEVEL>;
	status = "ok";
};

&video_cc_mvs0_gdsc {
	reg = <0xaaf809c 0x4>;
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&video_cc_mvs0c_gdsc {
	reg = <0xaaf804c 0x4>;
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&video_cc_mvs1_gdsc {
	reg = <0xaaf80c0 0x4>;
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";
};

&video_cc_mvs1c_gdsc {
	reg = <0xaaf8074 0x4>;
	clocks = <&gcc GCC_VIDEO_AHB_CLK>;
	clock-names = "ahb_clk";
	parent-supply = <&VDD_MM_MXC_VOTER_LEVEL>;
	status = "ok";

};

&qupv3_se2_i2c {
	status = "ok";
	fsa4480: fsa4480@42 {
		compatible = "qcom,fsa4480-i2c";
		reg = <0x42>;
	};
};

#include "anorak-usb.dtsi"
#include "anorak-pinctrl.dtsi"
#include "anorak-regulators.dtsi"
#include "anorak-dma-heaps.dtsi"
#include "ipcc-test.dtsi"
#include "anorak-pcie.dtsi"
#include "msm-arm-smmu-anorak.dtsi"
#include "anorak-coresight.dtsi"
#include "anorak-debug.dtsi"
#include "msm-rdbg.dtsi"
#include "anorak-gpu.dtsi"
#include "anorak-hsp.dtsi"
#include "anorak-thermal.dtsi"

