#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>

&soc {
	mdss_mdp: qcom,mdss_mdp@ae00000 {
		compatible = "qcom,sde-kms";
		reg = <0x0ae00000 0x84000>,
			<0x0aeb0000 0x2008>,
			<0x0aeac000 0x800>,
			<0x0ae8f000 0x30>;
		reg-names = "mdp_phys",
			"vbif_phys",
			"regdma_phys",
			"sid_phys";

		/* interrupt config */
		interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
		interrupt-controller;
		#interrupt-cells = <1>;
		#cooling-cells = <2>;

		/* hw blocks */
		qcom,sde-off = <0x1000>;
		qcom,sde-len = <0x494>;

		qcom,sde-ctl-off = <0x16000>;
		qcom,sde-ctl-size = <0x204>;
		qcom,sde-ctl-display-pref = "primary";

		qcom,sde-mixer-off = <0x45000>;

		qcom,sde-mixer-size = <0x400>;
		qcom,sde-mixer-display-pref = "primary";

		qcom,sde-dspp-top-off = <0x1300>;
		qcom,sde-dspp-top-size = <0x80>;
		qcom,sde-dspp-off = <0x55000>;
		qcom,sde-dspp-size = <0x1800>;

		qcom,sde-dspp-rc-version = <0x00010000>;
		qcom,sde-dspp-rc-off = <0x15800>;
		qcom,sde-dspp-rc-size = <0x100>;
		qcom,sde-dspp-rc-mem-size = <2720>;

		qcom,sde-intf-off = <0x0 0x36000>;
		qcom,sde-intf-size = <0x2c4>;
		qcom,sde-intf-type = "none", "dsi";
		qcom,sde-intf-tear-irq-off = <0x0 0x36800>;

		qcom,sde-pp-off = <0x6a000>;
		qcom,sde-pp-slave = <0x0>;
		qcom,sde-pp-size = <0xd4>;

		qcom,sde-dsc-off = <0x81000>;
		qcom,sde-dsc-size = <0x10>;
		qcom,sde-dsc-hw-rev = "dsc_1_2";
		qcom,sde-dsc-enc = <0x100>;
		qcom,sde-dsc-enc-size = <0x100>;
		qcom,sde-dsc-ctl = <0xF00>;
		qcom,sde-dsc-ctl-size = <0x10>;
		qcom,sde-dsc-native422-supp = <1>;
		qcom,sde-dsc-linewidth = <2560>;

		qcom,sde-dither-off = <0xe0>;
		qcom,sde-dither-version = <0x00020000>;
		qcom,sde-dither-size = <0x20>;

		qcom,sde-sspp-type = "vig", "dma";
		qcom,sde-sspp-off = <0x5000 0x25000>;
		qcom,sde-sspp-src-size = <0x328>;

		qcom,sde-sspp-xin-id = <0 1>;
		qcom,sde-sspp-excl-rect = <1 1>;
		qcom,sde-sspp-smart-dma-priority = <2 1>;
		qcom,sde-smart-dma-rev = "smart_dma_v2p5";

		qcom,sde-mixer-pair-mask = <0>;

		qcom,sde-mixer-blend-op-off = <0x20 0x38 0x50 0x68 0x80 0x98
						0xb0 0xc8 0xe0 0xf8 0x110>;
		qcom,sde-ddr-type = <0x8 0x7>;
		qcom,sde-max-per-pipe-bw-kbps = <4100000 4100000>,
						<3500000 3500000>;

		/* offsets are relative to "mdp_phys + qcom,sde-off */
		qcom,sde-sspp-clk-ctrl = <0x2ac 0>, <0x2ac 8>;
		qcom,sde-sspp-clk-status = <0x2b0 0>, <0x2b0 12>;
		qcom,sde-sspp-csc-off = <0x1a00>;
		qcom,sde-csc-type = "csc-10bit";
		qcom,sde-qseed-sw-lib-rev = "qseedv3lite";
		qcom,sde-qseed-scalar-version = <0x3001>;
		qcom,sde-sspp-qseed-off = <0xa00>;
		qcom,sde-mixer-linewidth = <2560>;
		qcom,sde-sspp-linewidth = <4096>;
		qcom,sde-vig-sspp-linewidth = <5120>;
		qcom,sde-mixer-blendstages = <5>;
		qcom,sde-highest-bank-bit = <0x8 0x2>,
					<0x7 0x1>;
		qcom,sde-ubwc-version = <0x200>;
		qcom,sde-ubwc-swizzle = <0x6>;
		qcom,sde-ubwc-bw-calc-version = <0x1>;
		qcom,sde-ubwc-static = <0x1>;
		qcom,sde-macrotile-mode = <0x0>;
		qcom,sde-smart-panel-align-mode = <0xc>;
		qcom,sde-panic-per-pipe;
		qcom,sde-has-cdp;
		qcom,sde-has-src-split;
		qcom,sde-pipe-order-version = <0x1>;
		qcom,sde-has-dim-layer;
		qcom,sde-max-trusted-vm-displays = <1>;

		qcom,sde-max-bw-low-kbps = <0x8 6400000>,
					<0x7 4200000>;
		qcom,sde-max-bw-high-kbps = <0x8 7400000>,
					<0x7 7000000>;
		qcom,sde-min-core-ib-kbps = <2500000>;
		qcom,sde-min-llcc-ib-kbps = <0>;
		qcom,sde-min-dram-ib-kbps = <1600000>;
		qcom,sde-dram-channels = <2>;
		qcom,sde-num-nrt-paths = <0>;
		qcom,sde-num-ddr-channels = <2>;

		qcom,sde-lm-noise-off = <0x320>;
		qcom,sde-lm-noise-version = <0x00010000>;

		qcom,sde-uidle-off = <0x80000>;
		qcom,sde-uidle-size = <0x70>;

		qcom,sde-vbif-off = <0>;
		qcom,sde-vbif-size = <0x1040>;
		qcom,sde-vbif-id = <0>;
		qcom,sde-vbif-memtype-0 = <3 3 3 3 3 3 3 3>;
		qcom,sde-vbif-memtype-1 = <3 3 3 3 3 3>;

		qcom,sde-vbif-default-ot-wr-limit = <32>;
		qcom,sde-vbif-dynamic-ot-wr-limit = <62208000 2 124416000 6 497664000 16>;

		qcom,sde-vbif-qos-rt-remap = <3 3 4 4 5 5 6 6>, <3 3 4 4 5 5 6 6>;
		qcom,sde-vbif-qos-lutdma-remap = <3 3 3 3 4 4 4 6>, <3 3 3 3 4 4 4 6>;

		qcom,sde-qos-refresh-rates = <120 240>;
		qcom,sde-danger-lut = <0x3fffff 0x3fffff 0x0 0x0 0x0 0x3ffffff 0x3ffffff>,
				<0x3ffffff 0x3ffffff 0x0 0x0 0x0 0x3ffffff 0x3ffffff>;

		qcom,sde-safe-lut = <0xF800 0xF800 0x0 0x0 0x0 0xE000 0xE000>,
				<0xE000 0xE000 0x0 0x0 0x0 0xE000 0xE000>;

		qcom,sde-creq-lut = <0x01223344 0x45566777 0x00112236 0x67777777
				0x01223344 0x45566777 0x00112236 0x67777777
				0x0        0x0        0x0        0x0
				0x0        0x0        0x0        0x0
				0x0        0x0        0x0        0x0
				0x00123445 0x56677777 0x00123667 0x77777777
				0x00123445 0x56677777 0x00123667 0x77777777>,
				<0x02344455 0x56667777 0x02366677 0x77777777
				0x02344455 0x56667777 0x02366677 0x77777777
				0x0        0x0        0x0        0x0
				0x0        0x0        0x0        0x0
				0x0        0x0        0x0        0x0
				0x02344455 0x56667777 0x02366677 0x77777777
				0x00123445 0x56677777 0x00123667 0x77777777>;

		qcom,sde-cdp-setting = <1 1>, <1 0>;

		qcom,sde-qos-cpu-mask = <0x3>;
		qcom,sde-qos-cpu-mask-performance = <0xf>;
		qcom,sde-qos-cpu-dma-latency = <300>;
		qcom,sde-qos-cpu-irq-latency = <300>;

		/* offsets are relative to "regdma_phys" */
		qcom,sde-reg-dma-off = <0 0x400>;
		qcom,sde-reg-dma-id = <0 1>;
		qcom,sde-reg-dma-version = <0x00020000>;
		qcom,sde-reg-dma-trigger-off = <0x119c>;
		qcom,sde-reg-dma-xin-id = <7>;
		qcom,sde-reg-dma-clk-ctrl = <0x2bc 20>;

		qcom,sde-secure-sid-mask = <0x0000801 0x0000c01>;

		qcom,sde-reg-bus,vectors-KBps = <0 0>,
						<0 74000>,
						<0 5000000>,
						<0 9700000>;

		qcom,sde-sspp-vig-blocks {
			vcm@0 {
				cell-index = <0>;
				qcom,sde-vig-top-off = <0xa00>;
				qcom,sde-vig-csc-off = <0x1a00>;
				qcom,sde-vig-qseed-off = <0xa00>;
				qcom,sde-vig-qseed-size = <0xe0>;
			};
		};

		qcom,sde-dspp-blocks {
			qcom,sde-dspp-igc = <0x1260 0x00040000>;
			qcom,sde-dspp-hsic = <0x800 0x00010007>;
			qcom,sde-dspp-memcolor = <0x880 0x00010007>;
			qcom,sde-dspp-hist = <0x800 0x00010007>;
			qcom,sde-dspp-sixzone = <0x900 0x00010007>;
			qcom,sde-dspp-vlut = <0xa00 0x00010008>;
			qcom,sde-dspp-pcc = <0x1700 0x00040000>;
			qcom,sde-dspp-gc = <0x17c0 0x00010008>;
			qcom,sde-dspp-dither = <0x82c 0x00010007>;
		};

	};

	mdss_dsi0: qcom,mdss_dsi_ctrl0@ae94000 {
		compatible = "qcom,dsi-ctrl-hw-v2.6";
		label = "dsi-ctrl-0";
		cell-index = <0>;
		frame-threshold-time-us = <800>;
		reg = <0xae94000 0x400>,
			<0xaf0f000 0x4>,
			<0x0ae36000 0x300>;
		reg-names = "dsi_ctrl", "disp_cc_base", "mdp_intf_base";
		interrupt-parent = <&mdss_mdp>;
		interrupts = <4 0>;
		qcom,split-link-supported;

		qcom,ctrl-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;

			qcom,ctrl-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-1p2";
				qcom,supply-min-voltage = <1200000>;
				qcom,supply-max-voltage = <1260000>;
				qcom,supply-enable-load = <16600>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	mdss_dsi_phy0: qcom,mdss_dsi_phy0@ae94900 {
		compatible = "qcom,dsi-phy-v4.3";
		label = "dsi-phy-0";
		cell-index = <0>;
		#clock-cells = <1>;
		reg = <0xae94400 0xa00>,
			<0xae94900 0x400>,
			<0xae94200 0xa0>;
		reg-names = "dsi_phy", "pll_base", "dyn_refresh_base";
		pll-label = "dsi_pll_5nm";

		qcom,platform-strength-ctrl = [55 03
						55 03
						55 03
						55 03
						55 00];
		qcom,platform-lane-config = [00 00 0a 0a
						00 00 0a 0a
						00 00 0a 0a
						00 00 0a 0a
						00 00 8a 8a];
		qcom,platform-regulator-settings = [1d 1d 1d 1d 1d];
		qcom,phy-supply-entries {
			#address-cells = <1>;
			#size-cells = <0>;
			qcom,phy-supply-entry@0 {
				reg = <0>;
				qcom,supply-name = "vdda-0p9";
				qcom,supply-min-voltage = <880000>;
				qcom,supply-max-voltage = <1052000>;
				qcom,supply-enable-load = <97800>;
				qcom,supply-disable-load = <0>;
			};
		};
	};

	dsi_pll_codes_data:dsi_pll_codes {
		reg = <0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0
			0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x0>;
		label = "dsi_pll_codes";
	};
};
