#include <dt-bindings/clock/mdss-5nm-pll-clk.h>
#include <dt-bindings/clock/qcom,gcc-ravelin.h>
#include <dt-bindings/clock/qcom,dispcc-ravelin.h>
#include "ravelin-sde-common.dtsi"

&soc {
	/* dummy display clock provider */
	clock_cpucc: qcom,cpucc {
		compatible = "qcom,dummycc";
		clock-output-names = "cpucc_clocks";
		#clock-cells = <1>;
	};

	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
                compatible = "qcom,smmu_sde_unsec";
                iommus = <&apps_smmu 0x0804 0x402>;
                qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
                qcom,iommu-faults = "non-fatal";
                dma-coherent;
        };
};

&mdss_mdp {
	reg = <0x0ae00000 0x84000>,
	      <0x0aeb0000 0x2008>,
	      <0x0aeac000 0x800>,
	      <0x0ae8f000 0x02c>;

	reg-names = "mdp_phys",
		"vbif_phys",
		"regdma_phys",
		"sid_phys";

	qcom,sde-vm-exclude-reg-names = "sid_phys";
	qcom,tvm-include-reg = <0xaf20000 0x4d68>,
				<0xaf30000 0x3fd4>;

	qcom,sde-hw-version =<0x80060000>;

	clocks = <&clock_cpucc GCC_DISP_HF_AXI_CLK>,
		<&clock_cpucc DISP_CC_MDSS_AHB_CLK>,
		<&clock_cpucc DISP_CC_MDSS_MDP_CLK>,
		<&clock_cpucc DISP_CC_MDSS_VSYNC_CLK>,
		<&clock_cpucc DISP_CC_MDSS_MDP_LUT_CLK>,
		<&clock_cpucc DISP_CC_MDSS_ROT_CLK>;
	clock-names = "gcc_bus", "iface_clk", "core_clk",
			"vsync_clk", "lut_clk", "rot_clk";
	qcom,sde-trusted-vm-env;
};

&mdss_dsi0 {
	clocks = <&clock_cpucc DISP_CC_MDSS_BYTE0_CLK>,
		<&clock_cpucc DISP_CC_MDSS_BYTE0_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK>,
		<&clock_cpucc DISP_CC_MDSS_PCLK0_CLK_SRC>,
		<&clock_cpucc DISP_CC_MDSS_ESC0_CLK>;
	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
			"pixel_clk", "pixel_clk_rcg", "esc_clk";
};

&mdss_dsi_phy0 {
	qcom,dsi-pll-in-trusted-vm;
};
