#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/clock/qcom,gcc-waipio.h>
#include <dt-bindings/clock/qcom,rpmh.h>

/ {
	#address-cells = <0x2>;
	#size-cells = <0x2>;
	qcom,msm-id = <457 0x10000>, <482 0x10000>;
	interrupt-parent = <&vgic>;

	qcom,mem-buf {
		compatible = "qcom,mem-buf";
		qcom,mem-buf-capabilities = "consumer";
		qcom,vmid = <45>;
	};

	qcom,mem-buf-msgq {
		compatible = "qcom,mem-buf-msgq";
	};

	chosen {
		bootargs = "nokaslr log_buf_len=256K root=/dev/ram rw init=/init console=hvc0 loglevel=8";
	};

	cpus {
		#address-cells = <0x2>;
		#size-cells = <0x0>;

		CPU0: cpu@0 {
			compatible = "arm,armv8";
			reg = <0x0 0x0>;
			device_type = "cpu";
			enable-method = "psci";
			cpu-idle-states = <&CPU_PWR_DWN
					   &CLUSTER_PWR_DWN>;
		};

		CPU1: cpu@100 {
			compatible = "arm,armv8";
			reg = <0x0 0x100>;
			device_type = "cpu";
			enable-method = "psci";
			cpu-idle-states = <&CPU_PWR_DWN
					   &CLUSTER_PWR_DWN>;
		};
	};

	idle-states {
		CPU_PWR_DWN: c4 {  /* Using Gold C4 latencies */
			compatible = "arm,idle-state";
			idle-state-name = "rail-pc";
			entry-latency-us = <600>;
			exit-latency-us = <1550>;
			min-residency-us = <4791>;
			arm,psci-suspend-param = <0x40000004>;
			local-timer-stop;
		};

		CLUSTER_PWR_DWN: d4 { /* C4+D4 */
			compatible = "arm,idle-state";
			idle-state-name = "l3-pc";
			entry-latency-us = <1050>;
			exit-latency-us = <2500>;
			min-residency-us = <5309>;
			arm,psci-suspend-param = <0x40000044>;
			local-timer-stop;
		};
	};

	qrtr-gunyah {
		compatible = "qcom,qrtr-gunyah";
		gunyah-label = <3>;
	};

	gunyah-vsock {
		compatible = "qcom,gunyah-vsock";
		qcom,master;
		msgq-label = <3>;
	};

	qcom,vm-config {
		compatible = "qcom,vm-1.0";
		vm-type = "aarch64-guest";
		boot-config = "fdt,unified";
		os-type = "linux";
		kernel-entry-segment = "kernel";
		kernel-entry-offset = <0x0 0x0>;
		vendor = "Qualcomm";
		image-name = "qcom,trustedvm";
		qcom,pasid = <0x0 0x1c>;
		qcom,qtee-config-info = "p=7C,8F,97,159,199,7F1;";
		qcom,secdomain-ids = <45>;
		qcom,primary-vm-index = <0>;
		vm-uri = "qualcomm.com/vmuid/trusted-ui";
		vm-guid = "3f4d154a-92d3-54d0-9241-08e34c8bc670";
		qcom,sensitive;

		iomemory-ranges = <0x0 0x92c000 0x0 0x92c000 0x0 0x4000 0x0
				0x0 0xc400000 0x0 0xc400000 0x0 0x3000 0x1
				0x0 0xc42d000 0x0 0xc42d000 0x0 0x4000 0x1
				0x0 0xc440000 0x0 0xc440000 0x0 0x80000 0x1
				0x0 0xc4c0000 0x0 0xc4c0000 0x0 0x10000 0x1
				0x0 0xae8f000 0x0 0xae8f000 0x0 0x1000 0x0>;

		gic-irq-ranges = <283 283>; /* PVM->SVM IRQ transfer */

		memory {
			#address-cells = <0x2>;
			#size-cells = <0x0>;
			base-address = <0x0 0xe0b00000>;
			size-min = <0x0 0x7a00000>;    /* 122 MB */
		};

		segments {
			ramdisk = <2>; /* 8MB */
		};

		vcpus {
			config = "/cpus";
			affinity = "static";
			affinity-map = <0x5 0x6>;
			sched-priority = <0>;       /* relative to PVM */
			sched-timeslice = <2000>;   /* in ms */
		};

		interrupts {
			config = &vgic;
		};

		vdevices {
			generate = "/hypervisor";
			rm-rpc {
				vdevice-type = "rm-rpc";
				generate = "/hypervisor/qcom,resource-mgr";
				console-dev;
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				qcom,label = <0x1>;
			};

			virtio-mmio@0 {
				vdevice-type = "virtio-mmio";
				generate = "/virtio-mmio";
				peer-default;
				vqs-num = <0x1>;
				push-compatible = "virtio,mmio";
				dma-coherent;
				dma_base = <0x0 0x0>;
				memory {
					qcom,label = <0x11>;
					#address-cells = <0x2>;
					base = <0x0 0xFFEFC000>;
				};
			};

			swiotlb-shm {
				vdevice-type = "shm";
				generate = "/swiotlb";
				push-compatible = "swiotlb";
				peer-default;
				dma_base = <0x0 0x4000>;
				memory {
					qcom,label = <0x12>;
					#address-cells = <0x2>;
					base = <0x0 0xFFF00000>;
				};
			};

			mem-buf-message-queue-pair {
				vdevice-type = "message-queue-pair";
				generate = "/hypervisor/membuf-msgq-pair";
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				peer-default;
				qcom,label = <0x0000001>;
			};

			display-message-queue-pair {
				vdevice-type = "message-queue-pair";
				generate = "/hypervisor/display-msgq-pair";
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				peer-default;
				qcom,label = <0x0000002>;
			};

			gvsock-message-queue-pair {
				vdevice-type = "message-queue-pair";
				generate = "/hypervisor/gvsock-msgq-pair";
				message-size = <0x000000f0>;
				queue-depth = <0x00000008>;
				peer = "vm-name:qcom,oemvm";
				qcom,label = <0x0000003>;
			};

			qrtr-shm {
				vdevice-type = "shm-doorbell";
				generate = "/hypervisor/qrtr-shm";
				push-compatible = "qcom,qrtr-gunyah-gen";
				peer-default;
				memory {
					qcom,label = <0x3>;
					allocate-base;
				};
			};

			gpiomem0 {
				vdevice-type = "iomem";
				patch = "/soc/tlmm-vm-mem-access";
				push-compatible = "qcom,tlmm-vm-mem-access";
				peer-default;
				memory {
					qcom,label = <0x8>;
					qcom,mem-info-tag = <0x2>;
					allocate-base;
				};
			};

			test-dbl {
				vdevice-type = "doorbell";
				generate = "/hypervisor/test-dbl";
				qcom,label = <0x4>;
				peer-default;
			};

			test-dbl-source {
				vdevice-type = "doorbell-source";
				generate = "/hypervisor/test-dbl-source";
				qcom,label = <0x4>;
				peer-default;
			};
		};
	};

	firmware: firmware {
		scm {
			compatible = "qcom,scm";
		};
	};

	soc: soc { };
};

&soc {
	#address-cells = <1>;
	#size-cells = <1>;
	ranges = <0 0 0 0xffffffff>;
	compatible = "simple-bus";

	spmi_bus: qcom,spmi@c42d000 {
		compatible = "qcom,spmi-pmic-arb";
		reg = <0xc42d000 0x4000>,
		      <0xc400000 0x3000>,
		      <0xc500000 0x400000>,
		      <0xc440000 0x80000>,
		      <0xc4c0000 0x10000>;
		reg-names = "cnfg", "core", "chnls", "obsrvr", "intr";
		#address-cells = <2>;
		#size-cells = <0>;
		cell-index = <0>;
		qcom,channel = <0>;
		qcom,ee = <0>;
		qcom,bus-id = <0>;
	};

	vm_tlmm_irq: vm-tlmm-irq@0 {
		compatible = "qcom,tlmm-vm-irq";
		reg = <0x0 0x0>;
		interrupt-controller;
		#interrupt-cells = <2>;
	};

	tlmm: pinctrl@f000000 {
		compatible = "qcom,waipio-vm-pinctrl";
		reg = <0x0F000000 0x1000000>;
		interrupts-extended = <&vm_tlmm_irq 1 IRQ_TYPE_LEVEL_HIGH>;
		gpio-controller;
		#gpio-cells = <2>;
		interrupt-controller;
		#interrupt-cells = <2>;
		/* Valid pins */
		gpios = /bits/ 16 <64 65 66 67 0 4 86 87 16 17 18 19 20 21>;
	};

	psci {
		compatible = "arm,psci-1.0";
		method = "smc";
	};

	tlmm-vm-mem-access {
		compatible = "qcom,tlmm-vm-mem-access";
		tlmm-vm-gpio-list = <365 366 367 368 301 305 387 388 317 318 319 320 321 322>;
	};

	vgic: interrupt-controller@17100000 {
		compatible = "arm,gic-v3";
		interrupt-controller;
		#interrupt-cells = <0x3>;
		#redistributor-regions = <1>;
		redistributor-stride = <0x0 0x40000>;
		reg = <0x17100000 0x10000>,     /* GICD */
		      <0x17180000 0x100000>;    /* GICR * 8 */
	};

	arch_timer: timer {
		compatible = "arm,armv8-timer";
		always-on;
		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>,
			     <GIC_PPI 12 (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_LOW)>;
		clock-frequency = <19200000>;
	};

	/*
	 * QUPv3 Instances
	 * North 4 : SE 4
	 */
	qup_iommu_group: qup_common_iommu_group {
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
	};

	/* QUPv3_0 wrapper instance: North QUP */
	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
		compatible = "qcom,qupv3-geni-se";
		reg = <0x9c0000 0x2000>;
		iommus = <&apps_smmu 0x5b8 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		dma-coherent;
		status = "ok";
	};

	/* GPI */
	gpi_dma0: qcom,gpi-dma@900000 {
		compatible = "qcom,gpi-dma";
		#dma-cells = <5>;
		reg = <0x900000 0x60000>;
		reg-names = "gpi-top";
		iommus = <&apps_smmu 0x5b8 0x0>;
		qcom,iommu-group = <&qup_iommu_group>;
		dma-coherent;
		interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>,
			<GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>;
		qcom,max-num-gpii = <12>;
		qcom,gpii-mask = <0x80>;
		qcom,ev-factor = <2>;
		qcom,gpi-ee-offset = <0x10000>;
		qcom,le-vm;
		status = "ok";
	};

	/* I2C SE */
	qupv3_se4_i2c: i2c@990000 {
		compatible = "qcom,i2c-geni";
		reg = <0x990000 0x4000>;
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&gpi_dma0 0 4 3 64 0>,
			<&gpi_dma0 1 4 3 64 0>;
		dma-names = "tx", "rx";
		qcom,wrapper-core = <&qupv3_0>;
		qcom,le-vm;
		status = "disabled";
	};

	qupv3_se4_spi: spi@990000 {
		compatible = "qcom,spi-geni";
		reg = <0x990000 0x4000>;
		reg-names = "se_phys";
		#address-cells = <1>;
		#size-cells = <0>;
		dmas = <&gpi_dma0 0 4 1 64 0>,
			<&gpi_dma0 1 4 1 64 0>;
		dma-names = "tx", "rx";
		spi-max-frequency = <50000000>;
		qcom,wrapper-core = <&qupv3_0>;
		qcom,le-vm;
		status = "disabled";
	};

	qcom_smcinvoke {
		compatible = "qcom,smcinvoke";
	};

	qtee_shmbridge {
		compatible = "qcom,tee-shared-memory-bridge";
		qcom,custom-bridge-size = <512>;
		qcom,support-hypervisor;
	};

	qcom,test-dbl {
		compatible = "qcom,gh-dbl";
		qcom,label = <0x4>;
	};
};

#include "waipio-vm-dma-heaps.dtsi"
#include "msm-arm-smmu-waipio-vm.dtsi"
