#include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
#include <dt-bindings/clock/qcom,dispcc-ravelin.h>
#include <dt-bindings/clock/qcom,gcc-ravelin.h>
#include <dt-bindings/interconnect/qcom,ravelin.h>
#include <dt-bindings/clock/qcom,rpmh.h>
#include "ravelin-sde-common.dtsi"

&soc {
	sde_rscc: qcom,sde_rscc@af20000 {
		cell-index = <0>;
		compatible = "qcom,sde-rsc";
		reg = <0xaf20000 0x4d68>,
			<0xaf30000 0x3fd4>;
		reg-names = "drv", "wrapper";
		qcom,sde-rsc-version = <4>;

		qcom,sde-dram-channels = <2>;

		vdd-supply = <&disp_cc_mdss_core_gdsc>;
		clocks = <&dispcc DISP_CC_MDSS_RSCC_VSYNC_CLK>,
			<&dispcc DISP_CC_MDSS_NON_GDSC_AHB_CLK>,
			<&dispcc DISP_CC_MDSS_RSCC_AHB_CLK>;
		clock-names = "vsync_clk", "gdsc_clk", "iface_clk";

		qcom,msm-bus,active-only;
		interconnects =
			<&mmss_noc MASTER_MDP_DISP &mc_virt SLAVE_EBI1_DISP>;
		interconnect-names = "qcom,sde-data-bus0";
	};

	mdss_rotator: qcom,mdss_rotator {
		compatible = "qcom,sde_rotator";
		reg = <0xae00000 0xac000>,
		      <0xaeb0000 0x2008>;


		reg-names = "mdp_phys",
			"rot_vbif_phys";

		#list-cells = <1>;
		qcom,mdss-rot-mode = <1>;
		qcom,mdss-highest-bank-bit = <0x8 0x2>,
					     <0x7 0x1>;
		clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>,
			 <&dispcc DISP_CC_MDSS_ROT_CLK>;
		clock-names = "iface_clk", "rot_clk";

		interrupt-parent = <&mdss_mdp>;
		interrupts = <2 0>;

		power-domains = <&mdss_mdp>;

		interconnects = <&mmss_noc MASTER_MDP &mc_virt SLAVE_EBI1>,
				<&gem_noc MASTER_APPSS_PROC
					&cnoc2 SLAVE_DISPLAY_CFG>;
		interconnect-names = "qcom,rot-data-bus0",
					"qcom,sde-reg-bus";
		qcom,sde-reg-bus,vectors-KBps = <0 0>,<0 76800>;

		/*Offline rotator RT setting */
		qcom,mdss-rot-parent = <&mdss_mdp 0>;
		qcom,mdss-rot-xin-id = <10 11>;

		/* Offline rotator QoS setting */
		qcom,mdss-rot-vbif-qos-setting = <3 3 3 3 3 3 3 3>;
		qcom,mdss-rot-cdp-setting = <1 1>;
		qcom,mdss-rot-qos-lut = <0x0 0x0 0x0 0x0>;
		qcom,mdss-rot-danger-lut = <0x0 0x0>;
		qcom,mdss-rot-safe-lut = <0x0000ffff 0x0000ffff>;
		qcom,mdss-rot-vbif-memtype = <3 3>;
		qcom,mdss-default-ot-rd-limit = <32>;
		qcom,mdss-default-ot-wr-limit = <32>;

		qcom,mdss-sbuf-headroom = <20>;

		smmu_rot_unsec: qcom,smmu_rot_unsec_cb {
			compatible = "qcom,smmu_sde_rot_unsec";
			iommus = <&apps_smmu 0x081C 0x400>;
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
			qcom,iommu-faults = "non-fatal";
			dma-coherent;
		};

		smmu_rot_sec: qcom,smmu_rot_sec_cb {
			compatible = "qcom,smmu_sde_rot_sec";
			iommus = <&apps_smmu 0x81D 0x0>,
					<&apps_smmu 0xC1D 0x0>;
			qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
			qcom,iommu-faults = "non-fatal";
			qcom,iommu-vmid = <0xa>;
			dma-coherent;
		};
	};

	smmu_sde_unsec: qcom,smmu_sde_unsec_cb {
		compatible = "qcom,smmu_sde_unsec";
		iommus = <&apps_smmu 0x0800 0x402>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-faults = "non-fatal";
		qcom,iommu-earlymap; /* for cont-splash */
		dma-coherent;
	};

	smmu_sde_sec: qcom,smmu_sde_sec_cb {
		compatible = "qcom,smmu_sde_sec";
		iommus = <&apps_smmu 0x0801 0x0>,
			<&apps_smmu 0xc01 0x0>;
		qcom,iommu-dma-addr-pool = <0x00020000 0xfffe0000>;
		qcom,iommu-faults = "non-fatal";
		qcom,iommu-vmid = <0xa>;
	};
};

&mdss_mdp {
	clocks =
		<&gcc GCC_DISP_HF_AXI_CLK>,
		<&dispcc DISP_CC_MDSS_AHB_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_VSYNC_CLK>,
		<&dispcc DISP_CC_MDSS_MDP_LUT_CLK>,
		<&dispcc DISP_CC_MDSS_ROT_CLK>;
	clock-names = "gcc_bus", "iface_clk",
			"branch_clk", "core_clk", "vsync_clk",
			"lut_clk", "rot_clk";
	clock-rate = <0 0 506000000 506000000 19200000 506000000 200000000>;
	clock-max-rate = <0 0 608000000 608000000 19200000 608000000 300000000>;

	#power-domain-cells = <0>;
	#list-cells = <1>;

	/* data and reg bus scale settings */
	interconnects = <&mmss_noc MASTER_MDP &gem_noc SLAVE_LLCC>,
			<&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>,
			<&gem_noc MASTER_APPSS_PROC
				&cnoc2 SLAVE_DISPLAY_CFG>;
	interconnect-names = "qcom,sde-data-bus0", "qcom,sde-ebi-bus",
				"qcom,sde-reg-bus";

	qcom,sde-ib-bw-vote = <2500000 0 1600000>;
	qcom,sde-has-idle-pc;
	qcom,sde-vm-exclude-reg-names = "sid_phys";
};

&disp_rsc {
	sde_rsc_rpmh {
		compatible = "qcom,sde-rsc-rpmh";
		cell-index = <0>;
	};
};

&mdss_dsi0 {
	vdda-1p2-supply = <&L16B>;
	clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>,
		<&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK>,
		<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>,
		<&dispcc DISP_CC_MDSS_ESC0_CLK>,
		<&rpmhcc RPMH_CXO_CLK>;
	clock-names = "byte_clk", "byte_clk_rcg", "byte_intf_clk",
			"pixel_clk", "pixel_clk_rcg", "esc_clk", "xo";
};

&mdss_dsi_phy0 {
	vdda-0p9-supply = <&L5B>;
	qcom,dsi-pll-ssc-en;
	qcom,dsi-pll-ssc-mode = "down-spread";
	pll_codes_region = <&dsi_pll_codes_data>;

};
