#include "cape-sde-display-common.dtsi"
#include <dt-bindings/clock/qcom,dispcc-waipio.h>

&soc {
	display_panel_avdd: display_gpio_regulator@1 {
		compatible = "qti-regulator-fixed";
		regulator-name = "display_panel_avdd";
		regulator-min-microvolt = <5500000>;
		regulator-max-microvolt = <5500000>;
		regulator-enable-ramp-delay = <233>;
		gpio = <&tlmm 186 0>;
		enable-active-high;
		regulator-boot-on;
		proxy-supply = <&display_panel_avdd>;
		qcom,proxy-consumer-enable;
		pinctrl-names = "default";
		pinctrl-0 = <&display_panel_avdd_default>;
	};

	sde_wb: qcom,wb-display@0 {
		compatible = "qcom,wb-display";
		cell-index = <0>;
		label = "wb_display";
	};

	disp_rdump_memory: disp_rdump_region@b8000000 {
		reg = <0xb8000000 0x01400000>;
		label = "disp_rdump_region";
	};
};

&reserved_memory {
	splash_memory: splash_region {
		reg = <0x0 0xb8000000 0x0 0x02b00000>;
		label = "cont_splash_region";
	};
};

&sde_dsi {
	clocks = <&mdss_dsi_phy0 0>,
			<&mdss_dsi_phy0 1>,
			<&mdss_dsi_phy1 2>,
			<&mdss_dsi_phy1 3>,
			 /*
			  * Currently the dsi clock handles are under the dsi
			  * controller DT node. As soon as the controller probe
			  * finishes, the dispcc sync state can get called before
			  * the dsi_display probe potentially disturbing the clock
			  * votes for cont_splash use case. Hence we are no longer
			  * protected by the component model in this case against the
			  * disp cc sync state getting triggered after the dsi_ctrl
			  * probe. To protect against this incorrect sync state trigger
			  * add this dummy MDP clk vote handle to the dsi_display
			  * DT node. Since the dsi_display driver does not parse
			  * MDP clock nodes, no actual vote shall be added and this
			  * change is done just to satisfy sync state requirements.
			  */
			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
			"pll_byte_clk1", "pll_dsi_clk1",
			"mdp_core_clk";

	vddio-supply = <&L12C>;
	vci-supply = <&L13C>;
	extvdd-supply = <&L1D>;
};

&sde_dsi1 {
	clocks = <&mdss_dsi_phy0 0>,
			<&mdss_dsi_phy0 1>,
			<&mdss_dsi_phy1 2>,
			<&mdss_dsi_phy1 3>,
			 /*
			  * Currently the dsi clock handles are under the dsi
			  * controller DT node. As soon as the controller probe
			  * finishes, the dispcc sync state can get called before
			  * the dsi_display probe potentially disturbing the clock
			  * votes for cont_splash use case. Hence we are no longer
			  * protected by the component model in this case against the
			  * disp cc sync state getting triggered after the dsi_ctrl
			  * probe. To protect against this incorrect sync state trigger
			  * add this dummy MDP clk vote handle to the dsi_display
			  * DT node. Since the dsi_display driver does not parse
			  * MDP clock nodes, no actual vote shall be added and this
			  * change is done just to satisfy sync state requirements.
			  */
			 <&clock_dispcc DISP_CC_MDSS_MDP_CLK>;
	clock-names = "pll_byte_clk0", "pll_dsi_clk0",
			"pll_byte_clk1", "pll_dsi_clk1",
			"mdp_core_clk";

	vddio-supply = <&L12C>;
	vci-supply = <&L13C>;
	extvdd-supply = <&L1D>;
};

&mdss_mdp {
	connectors = <&sde_dsi &sde_dsi1 &smmu_sde_unsec &smmu_sde_sec &sde_wb &sde_rscc &sde_dp>;
};

&dsi_r66451_amoled_cmd {
	qcom,ulps-enabled;
};

&dsi_r66451_amoled_cmd_cphy {
        qcom,ulps-enabled;
};

&dsi_r66451_amoled_120hz_cmd_cphy {
        qcom,ulps-enabled;
};

&dsi_r66451_amoled_144hz_cmd {
	qcom,ulps-enabled;
};

&dsi_r66451_amoled_144hz_cmd_cphy {
        qcom,ulps-enabled;
};

&dsi_sim_dsc_375_cmd {
	qcom,ulps-enabled;
};

&dsi_sim_dsc_10b_cmd {
	qcom,ulps-enabled;
};
