* Qualcomm Technologies, Inc. MSM CSI Phy

=======================
Required Node Structure
=======================
The camera CSIPHY node must be described in First level of device nodes. The
first level describe the overall CSIPHY node structure.

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First Level Node - CSIPHY device
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- cell-index: csiphy hardware core index
  Usage: required
  Value type: <u32>
  Definition: Should specify the Hardware index id.

- compatible
  Usage: required
  Value type: <string>
  Definition: Should be "qcom,csiphy-v1.0",
	"qcom,csiphy-v1.1", "qcom,csiphy-v1.2", "qcom,csiphy-v1.2.1",
	"qcom,csiphy-v1.2.2", "qcom,csiphy-v2.0", "qcom,csiphy-v1.2.2.2",
	"qcom,csiphy-v1.2.3", "qcom,csiphy-v2.0.1", "qcom,csiphy-v2.1.0",
	"qcom,csiphy-v1.2.4", "qcom,csiphy-v1.2.5", "qcom,csiphy".

- reg
  Usage: required
  Value type: <u32>
  Definition: offset and length of the register set
	for the device for the csiphy operating in
	compatible mode.

- reg-names
  Usage: required
  Value type: <string>
  Definition: Should specify relevant names to each
	reg property defined.

- reg-cam-base
  Usage: required
  Value type: <string>
  Definition: offset of CSIPHY in  camera hw block

- interrupts
  Usage: required
  Value type: <u32>
  Definition: Interrupt associated with CCI HW.

- interrupt-names
  Usage: required
  Value type: <string>
  Definition: Name of the interrupt.

- regulator-names
  Usage: required
  Value type: <string>
  Definition: name of the voltage regulators required for the device.

- gdscr-supply
  Usage: required
  Value type: <phandle>
  Definition: should contain gdsr regulator used for CSIPHY clocks.

- mipi-csi-vdd-supply
  Usage: required
  Value type: <phandle>
  Definition: should contain phandle for mipi-csi-vdd regulator used for
	CSIPHY device.

- csi-vdd-xxx-supply
  Usage: required
  Value type: <phandle>
  Definition: should contain phandles for csi-vdd-1p2 and csi-vdd-0p9
	regulators used for CSIPHY.

- csi-vdd-voltage
  Usage: required
  Value type: <u32>
  Definition: should contain required voltage for csi-vdd supply
	for CSIPHY.

- rgltr-cntrl-support
  Usage: required
  Value type: <empty>
  Definition: Flag to indicate whether regulator control support is
	enabled or not.

- rgltr-min-voltage
  Usage: required
  Value type: <u32>
  Definition: should contain required min voltage for gdsr, csi-vdd-1p2
	and csi-vdd-0p9 supply for CSIPHY.

- rgltr-max-voltage
  Usage: required
  Value type: <u32>
  Definition: should contain required max voltage for gdsr, csi-vdd-1p2
	and csi-vdd-0p9 supply for CSIPHY.

- rgltr-load-current
  Usage: required
  Value type: <u32>
  Definition: should contain peak current for gdsr, csi-vdd-1p2
	and csi-vdd-0p9 supply for CSIPHY.

- rgltr-enable-sync
  Usage: required
  Value type: <u8>
  Definition: Decides whether regulator enable should be done in sync
   for all the csiphys together or not.

- clocks
  Usage: required
  Value type: <phandle>
  Definition: all clock phandle and source clocks.

- clock-names
  Usage: required
  Value type: <string>
  Definition: List of clock names required for CSIPHY HW.

- clock-cntl-level
  Usage: required
  Value type: <string>
  Definition: All different clock level node can support.

- src-clock-name
  Usage: required
  Value type: <string>
  Definition: Source clock name.

- clock-rates
  Usage: required
  Value type: <u32>
  Definition: List of clock rates in Hz for CSIPHY HW.

- shared-clks
  Usage: optional
  Value type: <u32>
  Definition: List of 0 or 1 values indicating whether shared clk or not.

Example:

cam_csiphy0: qcom,csiphy0@ace4000 {
	cell-index = <0>;
	compatible = "qcom,csiphy-v2.1.0", "qcom,csiphy";
	reg = < 0x0ace4000 0x2000>;
	reg-names = "csiphy";
	reg-cam-base = <0xe4000>;
	interrupts = <GIC_SPI 477 IRQ_TYPE_LEVEL_HIGH>;
	interrupt-names = "csiphy0";
	gdscr-supply = <&cam_cc_titan_top_gdsc>;
	csi-vdd-1p2-supply = <&pm8350_l6>;
	csi-vdd-0p9-supply = <&pm8350_l5>;
	rgltr-cntrl-support;
	rgltr-enable-sync = <1>;
	regulator-names = "gdscr", "csi-vdd-1p2", "csi-vdd-0p9";
	rgltr-min-voltage = <0 1200000 880000>;
	rgltr-max-voltage = <0 1248000 912000>;
	rgltr-load-current = <0 54700 102000>;
	shared-clks = <1 0 0 0>;
	clocks = <&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
		<&clock_camcc CAM_CC_CSIPHY0_CLK>,
		<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
		<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK>;
	clock-names = "cphy_rx_clk_src",
		"csiphy0_clk",
		"csi0phytimer_clk_src",
		"csi0phytimer_clk";
	src-clock-name = "csi0phytimer_clk_src";
	clock-cntl-level = "nominal";
	clock-rates =
		<480000000 0 400000000 0>;
	status = "ok";
};
