# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
%YAML 1.2
---
$id: "http://devicetree.org/schemas/phy/phy-cadence-torrent.yaml#"
$schema: "http://devicetree.org/meta-schemas/core.yaml#"

title: Cadence Torrent SD0801 PHY binding for DisplayPort

description:
  This binding describes the Cadence SD0801 PHY (also known as Torrent PHY)
  hardware included with the Cadence MHDP DisplayPort controller.

maintainers:
  - Swapnil Jakhade <sjakhade@cadence.com>
  - Yuti Amonkar <yamonkar@cadence.com>

properties:
  compatible:
    enum:
      - cdns,torrent-phy
      - ti,j721e-serdes-10g

  '#address-cells':
    const: 1

  '#size-cells':
    const: 0

  clocks:
    maxItems: 1
    description:
      PHY reference clock. Must contain an entry in clock-names.

  clock-names:
    const: refclk

  reg:
    minItems: 1
    maxItems: 2
    items:
      - description: Offset of the Torrent PHY configuration registers.
      - description: Offset of the DPTX PHY configuration registers.

  reg-names:
    minItems: 1
    maxItems: 2
    items:
      - const: torrent_phy
      - const: dptx_phy

  resets:
    maxItems: 1
    description:
      Torrent PHY reset.
      See Documentation/devicetree/bindings/reset/reset.txt

patternProperties:
  '^phy@[0-7]+$':
    type: object
    description:
      Each group of PHY lanes with a single master lane should be represented as a sub-node.
    properties:
      reg:
        description:
          The master lane number. This is the lowest numbered lane in the lane group.

      resets:
        minItems: 1
        maxItems: 4
        description:
          Contains list of resets, one per lane, to get all the link lanes out of reset.

      "#phy-cells":
        const: 0

      cdns,phy-type:
        description:
          Specifies the type of PHY for which the group of PHY lanes is used.
          Refer include/dt-bindings/phy/phy.h. Constants from the header should be used.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [1, 2, 3, 4, 5, 6]

      cdns,num-lanes:
        description:
          Number of DisplayPort lanes.
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [1, 2, 4]
        default: 4

      cdns,max-bit-rate:
        description:
          Maximum DisplayPort link bit rate to use, in Mbps
        $ref: /schemas/types.yaml#/definitions/uint32
        enum: [2160, 2430, 2700, 3240, 4320, 5400, 8100]
        default: 8100

    required:
      - reg
      - resets
      - "#phy-cells"
      - cdns,phy-type

    additionalProperties: false

required:
  - compatible
  - "#address-cells"
  - "#size-cells"
  - clocks
  - clock-names
  - reg
  - reg-names
  - resets

additionalProperties: false

examples:
  - |
    #include <dt-bindings/phy/phy.h>

    bus {
        #address-cells = <2>;
        #size-cells = <2>;

        torrent-phy@f0fb500000 {
            compatible = "cdns,torrent-phy";
            reg = <0xf0 0xfb500000 0x0 0x00100000>,
                  <0xf0 0xfb030a00 0x0 0x00000040>;
            reg-names = "torrent_phy", "dptx_phy";
            resets = <&phyrst 0>;
            clocks = <&ref_clk>;
            clock-names = "refclk";
            #address-cells = <1>;
            #size-cells = <0>;
            phy@0 {
                      reg = <0>;
                      resets = <&phyrst 1>, <&phyrst 2>,
                               <&phyrst 3>, <&phyrst 4>;
                      #phy-cells = <0>;
                      cdns,phy-type = <PHY_TYPE_DP>;
                      cdns,num-lanes = <4>;
                      cdns,max-bit-rate = <8100>;
            };
        };
    };
...
