From 07cab36b8961b26fa842de5846b3b018d16c8df1 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Tue, 28 Jan 2020 00:07:32 +0530 Subject: [PATCH] ARM: dts: msm: Add initial device tree for Holi Adding initial device tree support for holi target. Change-Id: Id5bc80a3ba916424650c993b2a52d080b1a1b2cb --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 8 + qcom/holi-rumi-overlay.dts | 11 ++ qcom/holi-rumi.dts | 11 ++ qcom/holi-rumi.dtsi | 13 ++ qcom/holi.dts | 9 + qcom/holi.dtsi | 369 +++++++++++++++++++++++++++++++++++++ 7 files changed, 425 insertions(+) create mode 100644 qcom/holi-rumi-overlay.dts create mode 100644 qcom/holi-rumi.dts create mode 100644 qcom/holi-rumi.dtsi create mode 100644 qcom/holi.dts create mode 100644 qcom/holi.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index ce417ccb..03126d00 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -80,6 +80,9 @@ SoCs: - SDMMAGPIE compatible = "qcom,sdmmagpie" +- HOLI + compatible = "qcom,holi" + Generic board variants: - CDP device: @@ -216,3 +219,4 @@ compatible = "qcom,sdxprairie-cdp" compatible = "qcom,sdmmagpie-rumi" compatible = "qcom,sdmmagpie-idp" compatible = "qcom,sdmmagpie-qrd" +compatible = "qcom,holi-rumi" diff --git a/qcom/Makefile b/qcom/Makefile index e5bb5b21..f37a9a3e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -34,6 +34,14 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahainap-qrd.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo + +holi-rumi-overlay.dtbo-base := holi.dtb +else +dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo diff --git a/qcom/holi-rumi-overlay.dts b/qcom/holi-rumi-overlay.dts new file mode 100644 index 00000000..19d9f2ca --- /dev/null +++ b/qcom/holi-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "holi-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi RUMI"; + compatible = "qcom,holi-rumi", "qcom,holi", "qcom,rumi"; + qcom,msm-id = <454 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/holi-rumi.dts b/qcom/holi-rumi.dts new file mode 100644 index 00000000..09a7fd44 --- /dev/null +++ b/qcom/holi-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x50000000 0x00000100; + +#include "holi.dtsi" +#include "holi-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi RUMI"; + compatible = "qcom,holi-rumi", "qcom,holi", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/holi-rumi.dtsi b/qcom/holi-rumi.dtsi new file mode 100644 index 00000000..86d4cf1f --- /dev/null +++ b/qcom/holi-rumi.dtsi @@ -0,0 +1,13 @@ +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@f420000 { + clock-frequency = <500000>; + }; + + wdog { + status = "disabled"; + }; +}; diff --git a/qcom/holi.dts b/qcom/holi.dts new file mode 100644 index 00000000..742e8293 --- /dev/null +++ b/qcom/holi.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "holi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi SoC"; + compatible = "qcom,holi"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi new file mode 100644 index 00000000..e13f2038 --- /dev/null +++ b/qcom/holi.dtsi @@ -0,0 +1,369 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Holi"; + compatible = "qcom,holi"; + qcom,msm-id = <454 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cache-size = <0x10000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cache-size = <0x10000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + + }; + }; + + soc: soc { }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf240000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f420000 0x1000>; + clock-frequency = <19200000>; + + frame@f421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + }; + + frame@f423000 { + frame-number = <1>; + interrupts = ; + reg = <0xf243000 0x1000>; + status = "disabled"; + }; + + frame@f425000 { + frame-number = <2>; + interrupts = ; + reg = <0xf425000 0x1000>; + status = "disabled"; + }; + + frame@f427000 { + frame-number = <3>; + interrupts = ; + reg = <0xf427000 0x1000>; + status = "disabled"; + }; + + frame@f429000 { + frame-number = <4>; + interrupts = ; + reg = <0xf429000 0x1000>; + status = "disabled"; + }; + + frame@f42b000 { + frame-number = <5>; + interrupts = ; + reg = <0xf42b000 0x1000>; + status = "disabled"; + }; + + frame@f42d000 { + frame-number = <6>; + interrupts = ; + reg = <0xf42d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + wdog: qcom,wdt@f410000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf410000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + ipcc_mproc: qcom,ipcc@208000 { + compatible = "qcom,ipcc"; + reg = <0x208000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; +};