From fc54917e393f5e50d86cc35ffc8082d4c27ac881 Mon Sep 17 00:00:00 2001
From: Zhenhua Huang <zhenhuah@qti.qualcomm.com>
Date: Thu, 16 Jun 2022 21:18:38 +0800
Subject: [PATCH] ARM: dts: msm: Correct some Context bank interrupts

Correct two content bank interrupts according to interrupt
selftests.

Change-Id: I9cf87b11918ded2edff9ba89dd14c9be0ce6e069
---
 qcom/msm-arm-smmu-ravelin.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi
index 2cfb1d57..6b6ce8ed 100644
--- a/qcom/msm-arm-smmu-ravelin.dtsi
+++ b/qcom/msm-arm-smmu-ravelin.dtsi
@@ -72,8 +72,8 @@
 				<GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 671 IRQ_TYPE_LEVEL_HIGH>,
-				<GIC_SPI 672 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>,
 				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,