From 0f0af0a543a2b0d1cc7d5cf5f96f8661d46f8244 Mon Sep 17 00:00:00 2001 From: Odelu Kukatla Date: Mon, 7 Sep 2020 00:40:20 +0530 Subject: [PATCH] ARM: dts: msm: Add handles for PCIE clocks PCIE cocks need to be enabled for QoS settings programming, so add PCIE clock handles. Change-Id: I882f07b33b3e7ffaaabeaca258831b8ac0757973 --- qcom/shima-pcie.dtsi | 2 +- qcom/shima.dtsi | 8 ++++---- 2 files changed, 5 insertions(+), 5 deletions(-) diff --git a/qcom/shima-pcie.dtsi b/qcom/shima-pcie.dtsi index 4a05eff1..32573d6d 100644 --- a/qcom/shima-pcie.dtsi +++ b/qcom/shima-pcie.dtsi @@ -59,7 +59,7 @@ RPMH_REGULATOR_LEVEL_NOM 100000000>; /* Gen3 */ interconnect-names = "icc_path"; - interconnects = <&aggre2_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; + interconnects = <&aggre1_noc MASTER_PCIE_0 &mc_virt SLAVE_EBI1>; clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, <&rpmhcc RPMH_CXO_CLK>, diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index 4170db3d..7fb43f4b 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -2052,7 +2052,9 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; }; @@ -2062,9 +2064,7 @@ #interconnect-cells = <1>; qcom,bcm-voter-names = "hlos"; qcom,bcm-voters = <&apps_bcm_voter>; - clocks = <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>, - <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, - <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, + clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, <&rpmhcc RPMH_IPA_CLK>; };