From 0f4eb65a97cfcf9b7f093d20b84e1de8ef7fa910 Mon Sep 17 00:00:00 2001
From: Pratham Pratap <ppratap@qti.qualcomm.com>
Date: Thu, 19 Mar 2020 14:41:20 +0530
Subject: [PATCH] ARM: dts: msm: Add USB nodes for Shima

Add USB nodes to support USB in peripheral mode on
simulation platforms for Shima.

Change-Id: I9ea4cded7b55293a12a9d0305cc3d210f20780ec
---
 qcom/shima-rumi.dtsi | 23 +++++++++++++++
 qcom/shima-usb.dtsi  | 67 ++++++++++++++++++++++++++++++++++++++++++++
 qcom/shima.dtsi      |  1 +
 3 files changed, 91 insertions(+)
 create mode 100644 qcom/shima-usb.dtsi

diff --git a/qcom/shima-rumi.dtsi b/qcom/shima-rumi.dtsi
index 0987448b..7a012a61 100644
--- a/qcom/shima-rumi.dtsi
+++ b/qcom/shima-rumi.dtsi
@@ -10,4 +10,27 @@
 	wdog: qcom,wdt@17c10000 {
 		status = "disabled";
 	};
+
+	usb_emu_phy_0: usb_emu_phy@a720000 {
+		compatible = "qcom,usb-emu-phy";
+		reg = <0x0a720000 0x9500>;
+
+		qcom,emu-init-seq = <0xffff 0x4
+				     0xfff0 0x4
+				     0x100000 0x20
+				     0x0 0x20
+				     0x101f0 0x20
+				     0x100000 0x3c
+				     0x0 0x3c
+				     0x10060 0x3c
+				     0x0 0x4>;
+	};
+};
+
+&usb0 {
+	dwc3@a600000 {
+		usb-phy = <&usb_emu_phy_0>, <&usb_nop_phy>;
+		maximum-speed = "high-speed";
+		dr_mode = "peripheral";
+	};
 };
diff --git a/qcom/shima-usb.dtsi b/qcom/shima-usb.dtsi
new file mode 100644
index 00000000..cb1913fa
--- /dev/null
+++ b/qcom/shima-usb.dtsi
@@ -0,0 +1,67 @@
+#include <dt-bindings/clock/qcom,gcc-shima.h>
+
+&soc {
+	usb0: ssusb@a600000 {
+		compatible = "qcom,dwc-usb3-msm";
+		reg = <0xa600000 0x100000>;
+		reg-names = "core_base";
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+		ranges;
+
+		interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>,
+			     <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
+			     <&pdc 15 IRQ_TYPE_EDGE_RISING>;
+		interrupt-names = "dp_hs_phy_irq", "pwr_event_irq",
+				"ss_phy_irq", "dm_hs_phy_irq";
+		qcom,use-pdc-interrupts;
+
+		USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>;
+		clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>,
+			<&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
+			<&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
+			<&gcc GCC_USB30_PRIM_SLEEP_CLK>;
+		clock-names = "core_clk", "iface_clk", "bus_aggr_clk",
+					"utmi_clk", "sleep_clk";
+
+		resets = <&gcc GCC_USB30_PRIM_BCR>;
+		reset-names = "core_reset";
+
+		qcom,core-clk-rate = <200000000>;
+		qcom,core-clk-rate-hs = <66666667>;
+		qcom,num-gsi-evt-buffs = <0x3>;
+		qcom,gsi-reg-offset =
+			<0x0fc /* GSI_GENERAL_CFG */
+			0x110 /* GSI_DBL_ADDR_L */
+			0x120 /* GSI_DBL_ADDR_H */
+			0x130 /* GSI_RING_BASE_ADDR_L */
+			0x144 /* GSI_RING_BASE_ADDR_H */
+			0x1a4>; /* GSI_IF_STS */
+		qcom,dwc-usb3-msm-tx-fifo-size = <27696>;
+
+		dwc3@a600000 {
+			compatible = "snps,dwc3";
+			reg = <0xa600000 0xd93c>;
+			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
+			linux,sysdev_is_parent;
+			snps,disable-clk-gating;
+			snps,has-lpm-erratum;
+			snps,hird-threshold = /bits/ 8 <0x10>;
+			snps,dis-u1-entry-quirk;
+			snps,dis-u2-entry-quirk;
+			snps,dis_u2_susphy_quirk;
+			snps,dis_enblslpm_quirk;
+			tx-fifo-resize;
+			maximum-speed = "super-speed-plus";
+			dr_mode = "otg";
+		};
+	};
+
+	usb_nop_phy: usb_nop_phy {
+		compatible = "usb-nop-xceiv";
+	};
+
+};
diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi
index 490064c4..703e3990 100644
--- a/qcom/shima.dtsi
+++ b/qcom/shima.dtsi
@@ -838,6 +838,7 @@
 #include "shima-stub-regulator.dtsi"
 #include "shima-gdsc.dtsi"
 #include "shima-ion.dtsi"
+#include "shima-usb.dtsi"
 
 &gcc_pcie_0_gdsc {
 	status = "ok";