From 0fe72f90685b9ac9f25aa2902b9a6b1c85a11e15 Mon Sep 17 00:00:00 2001
From: David Collins <collinsd@quicinc.com>
Date: Mon, 2 Dec 2019 17:02:52 -0800
Subject: [PATCH] ARM: dts: msm: add SPMI debug bus for Lahaina boards

Add an SPMI debug bus device and associated child devices so that
consumers can have unrestricted access to the PMICs on
pre-production devices.  This helps to make debugging easier.

Change-Id: Ie0e7150bedd3b791344acaafd9f557dd9e1ff302
---
 qcom/lahaina-cdp.dtsi  |  4 +++
 qcom/lahaina-mtp.dtsi  |  4 +++
 qcom/lahaina-qrd.dtsi  |  4 +++
 qcom/lahaina-rumi.dtsi |  4 +++
 qcom/lahaina.dtsi      | 61 ++++++++++++++++++++++++++++++++++++++++++
 5 files changed, 77 insertions(+)

diff --git a/qcom/lahaina-cdp.dtsi b/qcom/lahaina-cdp.dtsi
index c9c8940c..2e3ab49d 100644
--- a/qcom/lahaina-cdp.dtsi
+++ b/qcom/lahaina-cdp.dtsi
@@ -1 +1,5 @@
 #include "lahaina-pmic-overlay.dtsi"
+
+&spmi_debug_bus {
+	status = "ok";
+};
diff --git a/qcom/lahaina-mtp.dtsi b/qcom/lahaina-mtp.dtsi
index c9c8940c..2e3ab49d 100644
--- a/qcom/lahaina-mtp.dtsi
+++ b/qcom/lahaina-mtp.dtsi
@@ -1 +1,5 @@
 #include "lahaina-pmic-overlay.dtsi"
+
+&spmi_debug_bus {
+	status = "ok";
+};
diff --git a/qcom/lahaina-qrd.dtsi b/qcom/lahaina-qrd.dtsi
index c9c8940c..2e3ab49d 100644
--- a/qcom/lahaina-qrd.dtsi
+++ b/qcom/lahaina-qrd.dtsi
@@ -1 +1,5 @@
 #include "lahaina-pmic-overlay.dtsi"
+
+&spmi_debug_bus {
+	status = "ok";
+};
diff --git a/qcom/lahaina-rumi.dtsi b/qcom/lahaina-rumi.dtsi
index 268916be..25f5de69 100644
--- a/qcom/lahaina-rumi.dtsi
+++ b/qcom/lahaina-rumi.dtsi
@@ -1,6 +1,10 @@
 #include "lahaina.dtsi"
 #include "lahaina-pmic-overlay.dtsi"
 
+&spmi_debug_bus {
+	status = "ok";
+};
+
 &ufsphy_mem {
 	compatible = "qcom,ufs-phy-qrbtc-sdm845";
 
diff --git a/qcom/lahaina.dtsi b/qcom/lahaina.dtsi
index b58c7b57..ccb480bd 100644
--- a/qcom/lahaina.dtsi
+++ b/qcom/lahaina.dtsi
@@ -10,6 +10,7 @@
 #include <dt-bindings/interconnect/qcom,lahaina.h>
 #include <dt-bindings/soc/qcom,ipcc.h>
 #include <dt-bindings/soc/qcom,rpmh-rsc.h>
+#include <dt-bindings/spmi/spmi.h>
 #include <dt-bindings/regulator/qcom,rpmh-regulator-levels.h>
 #include <dt-bindings/gpio/gpio.h>
 
@@ -1203,6 +1204,66 @@
 		qcom,ee = <0>;
 	};
 
+	spmi_debug_bus: qcom,spmi-debug@6b12000 {
+		compatible = "qcom,spmi-pmic-arb-debug";
+		reg = <0x6b12000 0x60>, <0x7820a8 0x4>;
+		reg-names = "core", "fuse";
+		clocks = <&clock_aop QDSS_CLK>;
+		clock-names = "core_clk";
+		qcom,fuse-disable-bit = <24>;
+		#address-cells = <2>;
+		#size-cells = <0>;
+		status = "disabled";
+
+		qcom,pmk8350-debug@0 {
+			compatible = "qcom,spmi-pmic";
+			reg = <0 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350-debug@1 {
+			compatible = "qcom,spmi-pmic";
+			reg = <1 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350c-debug@2 {
+			compatible = "qcom,spmi-pmic";
+			reg = <2 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pm8350b-debug@3 {
+			compatible = "qcom,spmi-pmic";
+			reg = <3 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pmr735a-debug@4 {
+			compatible = "qcom,spmi-pmic";
+			reg = <4 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+
+		qcom,pmr735b-debug@5 {
+			compatible = "qcom,spmi-pmic";
+			reg = <5 SPMI_USID>;
+			#address-cells = <2>;
+			#size-cells = <0>;
+			qcom,can-sleep;
+		};
+	};
+
 	qcom,msm-cdsp-loader {
 		compatible = "qcom,cdsp-loader";
 		qcom,proc-img-to-load = "cdsp";