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+Qualcomm Technologies, Inc. I2C PMIC Interrupt Controller
+Platform Independent Bindings
+
+The I2C PMIC Controller is used by multi-function PMIC devices which communicate
+over the I2C bus. An I2C PMIC controller node typically contains one or more
+child nodes representing the device's peripherals. Each of the peripherals
+typically has its own driver on the platform bus and will be enumerated by this
+controller. The controller exposes a regmap to the peripherals to communicate
+over the I2C bus.
+
+The controller also controls interrupts for all of the peripherals on the bus.
+The controller takes a summary interrupt, deciphers which peripheral triggered
+the interrupt, and which of the peripheral's interrupts were triggered. Finally,
+it calls the handlers for each of the virtual interrupts that were registered.
+
+This document describes the common platform independent bindings that apply
+to all I2C PMIC interrupt controllers.
+
+========================================
+First Level Nodes - I2C PMIC Controllers
+========================================
+
+Platform independent properties:
+- compatible
+	Usage:      required
+	Value type: <string>
+	Definition: Must be "qcom,i2c-pmic".
+
+- reg
+	Usage:      required
+	Value type: <u32>
+	Definition: 7-bit I2C address of the device.
+
+- interrupt-parent
+	Usage:      optional
+	Value type: <phandle>
+	Definition: phandle of the interrupt controller which services the
+		    summary interrupt.
+
+- interrupts
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: Summary interrupt specifier.
+
+- interrupt-controller
+	Usage:      optional
+	Value type: <empty>
+	Definition: Boolean flag which indicates this device node is an
+		    interrupt controller.
+
+- #interrupt-cells
+	Usage:      optional
+	Value type: <u32>
+	Definition: Number of cells to encode an interrupt source.
+
+- qcom,periph-map
+	Usage:      optional
+	Value type: <prop-encoded-array>
+	Definition: A list of u32 arrays. This provides a mapping between the
+		    summary status register bits and peripheral addresses.
+
+		    The number of arrays should match the number of summary
+		    registers with up to 8 elements each. One element per bit
+		    of the summary status register in order from the least
+		    sigificant bit to the most significant bit.
+
+- pinctrl-names
+	Usage:      optional
+	Value type: <string-list>
+	Definition: Should be "default".
+		    Please refer to pinctrl-bindings.txt
+
+- pinctrl-0
+	Usage:      optional
+	Value type: <phandle-list>
+	Definition: phandle of the pin configuration.
+		    Please refer to pinctrl-bindings.txt
+
+=======
+Example
+=======
+
+&i2c_3 {
+	status = "ok";
+	qcom,smb138x@8 {
+		compatible = "qcom,i2c-pmic";
+		reg = <0x8>;
+		interrupt-parent = <&tlmm_pinmux>;
+		interrupts = <83 0>;
+		interrupt-controller;
+		#interrupt-cells = <3>;
+		pinctrl-names = "default";
+		pinctrl-0 = <&smb_stat_active>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		qcom,periph-map = <0x10 0x11 0x12 0x13 0x14 0x16 0x36>;
+	};
+};