From 07cab36b8961b26fa842de5846b3b018d16c8df1 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Tue, 28 Jan 2020 00:07:32 +0530 Subject: [PATCH 1/2] ARM: dts: msm: Add initial device tree for Holi Adding initial device tree support for holi target. Change-Id: Id5bc80a3ba916424650c993b2a52d080b1a1b2cb --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 8 + qcom/holi-rumi-overlay.dts | 11 ++ qcom/holi-rumi.dts | 11 ++ qcom/holi-rumi.dtsi | 13 ++ qcom/holi.dts | 9 + qcom/holi.dtsi | 369 +++++++++++++++++++++++++++++++++++++ 7 files changed, 425 insertions(+) create mode 100644 qcom/holi-rumi-overlay.dts create mode 100644 qcom/holi-rumi.dts create mode 100644 qcom/holi-rumi.dtsi create mode 100644 qcom/holi.dts create mode 100644 qcom/holi.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index ce417ccb..03126d00 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -80,6 +80,9 @@ SoCs: - SDMMAGPIE compatible = "qcom,sdmmagpie" +- HOLI + compatible = "qcom,holi" + Generic board variants: - CDP device: @@ -216,3 +219,4 @@ compatible = "qcom,sdxprairie-cdp" compatible = "qcom,sdmmagpie-rumi" compatible = "qcom,sdmmagpie-idp" compatible = "qcom,sdmmagpie-qrd" +compatible = "qcom,holi-rumi" diff --git a/qcom/Makefile b/qcom/Makefile index e5bb5b21..f37a9a3e 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -34,6 +34,14 @@ dtb-$(CONFIG_ARCH_LAHAINA) += lahaina-rumi.dtb \ lahainap-qrd.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) + dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo + +holi-rumi-overlay.dtbo-base := holi.dtb +else +dtb-$(CONFIG_ARCH_HOLI) += holi-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_SHIMA) += \ shima-rumi-overlay.dtbo diff --git a/qcom/holi-rumi-overlay.dts b/qcom/holi-rumi-overlay.dts new file mode 100644 index 00000000..19d9f2ca --- /dev/null +++ b/qcom/holi-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "holi-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi RUMI"; + compatible = "qcom,holi-rumi", "qcom,holi", "qcom,rumi"; + qcom,msm-id = <454 0x10000>; + qcom,board-id = <15 0>; +}; diff --git a/qcom/holi-rumi.dts b/qcom/holi-rumi.dts new file mode 100644 index 00000000..09a7fd44 --- /dev/null +++ b/qcom/holi-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x50000000 0x00000100; + +#include "holi.dtsi" +#include "holi-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi RUMI"; + compatible = "qcom,holi-rumi", "qcom,holi", "qcom,rumi"; + qcom,board-id = <15 0>; +}; diff --git a/qcom/holi-rumi.dtsi b/qcom/holi-rumi.dtsi new file mode 100644 index 00000000..86d4cf1f --- /dev/null +++ b/qcom/holi-rumi.dtsi @@ -0,0 +1,13 @@ +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@f420000 { + clock-frequency = <500000>; + }; + + wdog { + status = "disabled"; + }; +}; diff --git a/qcom/holi.dts b/qcom/holi.dts new file mode 100644 index 00000000..742e8293 --- /dev/null +++ b/qcom/holi.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "holi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Holi SoC"; + compatible = "qcom,holi"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi new file mode 100644 index 00000000..e13f2038 --- /dev/null +++ b/qcom/holi.dtsi @@ -0,0 +1,369 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Holi"; + compatible = "qcom,holi"; + qcom,msm-id = <454 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-size = <0x100000>; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + cache-size = <0x8000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x10000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + cache-size = <0x10000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + cache-size = <0x10000>; + cpu-release-addr = <0x0 0x50000000>; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-size = <0x40000>; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + + core4 { + cpu = <&CPU4>; + }; + + core5 { + cpu = <&CPU5>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU6>; + }; + + core1 { + cpu = <&CPU7>; + }; + }; + + }; + }; + + soc: soc { }; + + chosen { + bootargs = "rcupdate.rcu_expedited=1 rcu_nocbs=0-7"; + }; + +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + intc: interrupt-controller@f200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0xf200000 0x10000>, /* GICD */ + <0xf240000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@f420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x0f420000 0x1000>; + clock-frequency = <19200000>; + + frame@f421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x0f421000 0x1000>, + <0x0f422000 0x1000>; + }; + + frame@f423000 { + frame-number = <1>; + interrupts = ; + reg = <0xf243000 0x1000>; + status = "disabled"; + }; + + frame@f425000 { + frame-number = <2>; + interrupts = ; + reg = <0xf425000 0x1000>; + status = "disabled"; + }; + + frame@f427000 { + frame-number = <3>; + interrupts = ; + reg = <0xf427000 0x1000>; + status = "disabled"; + }; + + frame@f429000 { + frame-number = <4>; + interrupts = ; + reg = <0xf429000 0x1000>; + status = "disabled"; + }; + + frame@f42b000 { + frame-number = <5>; + interrupts = ; + reg = <0xf42b000 0x1000>; + status = "disabled"; + }; + + frame@f42d000 { + frame-number = <6>; + interrupts = ; + reg = <0xf42d000 0x1000>; + status = "disabled"; + }; + }; + + cpu_pmu: cpu-pmu { + compatible = "arm,armv8-pmuv3"; + qcom,irq-is-percpu; + interrupts = ; + }; + + qcom,msm-imem@c125000 { + compatible = "qcom,msm-imem"; + reg = <0xc125000 0x1000>; + ranges = <0x0 0xc125000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + + mem_dump_table@10 { + compatible = "qcom,msm-imem-mem_dump_table"; + reg = <0x10 0x8>; + }; + + restart_reason@65c { + compatible = "qcom,msm-imem-restart_reason"; + reg = <0x65c 0x4>; + }; + + dload_type@1c { + compatible = "qcom,msm-imem-dload-type"; + reg = <0x1c 0x4>; + }; + + boot_stats@6b0 { + compatible = "qcom,msm-imem-boot_stats"; + reg = <0x6b0 0x20>; + }; + + kaslr_offset@6d0 { + compatible = "qcom,msm-imem-kaslr_offset"; + reg = <0x6d0 0xc>; + }; + + pil@94c { + compatible = "qcom,msm-imem-pil"; + reg = <0x94c 0xc8>; + }; + + diag_dload@c8 { + compatible = "qcom,msm-imem-diag-dload"; + reg = <0xc8 0xc8>; + }; + }; + + restart@440b000 { + compatible = "qcom,pshold"; + reg = <0x440b000 0x4>, <0x03d3000 0x4>; + reg-names = "pshold-base", "tcsr-boot-misc-detect"; + }; + + qcom,msm-rtb { + compatible = "qcom,msm-rtb"; + qcom,rtb-size = <0x100000>; + }; + + wdog: qcom,wdt@f410000 { + compatible = "qcom,msm-watchdog"; + reg = <0xf410000 0x1000>; + reg-names = "wdt-base"; + interrupts = <0 0 IRQ_TYPE_LEVEL_HIGH>, + <0 1 IRQ_TYPE_LEVEL_HIGH>; + qcom,bark-time = <11000>; + qcom,pet-time = <9360>; + qcom,ipi-ping; + qcom,wakeup-enable; + }; + + ipcc_mproc: qcom,ipcc@208000 { + compatible = "qcom,ipcc"; + reg = <0x208000 0x1000>; + interrupts = ; + interrupt-controller; + #interrupt-cells = <3>; + #mbox-cells = <2>; + }; +}; From a903a9f7788ed5082836386495980ffa3f095a62 Mon Sep 17 00:00:00 2001 From: Yogesh Lal Date: Wed, 5 Feb 2020 17:25:16 +0530 Subject: [PATCH 2/2] dt-bindings: Adding pinctrl devicetree binding for holi Adding pinctrl devicetree binding for holi platform. Change-Id: Ic8999b2360524e1178c2a63b4a8723fac0f22985 --- bindings/pinctrl/qcom,holi-pinctrl.yaml | 195 ++++++++++++++++++++++++ 1 file changed, 195 insertions(+) create mode 100644 bindings/pinctrl/qcom,holi-pinctrl.yaml diff --git a/bindings/pinctrl/qcom,holi-pinctrl.yaml b/bindings/pinctrl/qcom,holi-pinctrl.yaml new file mode 100644 index 00000000..90a209b3 --- /dev/null +++ b/bindings/pinctrl/qcom,holi-pinctrl.yaml @@ -0,0 +1,195 @@ +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/bindings/pinctrl/qcom,holi-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Technologies, Inc. HOLI TLMM block + +description: | + This binding describes the Top Level Mode Multiplexer block found in the + HOLI platform. + +properties: + compatible: + Usage: required + Value type: + Definition: must be "qcom,holi-pinctrl" + + reg: + Usage: required + Value type: + Definition: the base address and size of the TLMM register space. + + interrupts: + Usage: required + Value type: + Definition: should specify the TLMM summary IRQ. + + interrupt-controller: + Usage: required + Value type: + Definition: identifies this node as an interrupt controller + + #interrupt-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + gpio-controller: + Usage: required + Value type: + Definition: identifies this node as a gpio controller + + #gpio-cells: + Usage: required + Value type: + Definition: must be 2. Specifying the pin number and flags, as defined + in + + wakeup-parent: + Usage: optional + Value type: + Definition: A phandle to the wakeup interrupt controller for the SoC. + + Please refer to ../gpio/gpio.txt and ../interrupt-controller/interrupts.txt for + a general description of GPIO and interrupt bindings. + + Please refer to pinctrl-bindings.txt in this directory for details of the + common pinctrl bindings used by client devices, including the meaning of the + phrase "pin configuration node". + + The pin configuration nodes act as a container for an arbitrary number of + subnodes. Each of these subnodes represents some desired configuration for a + pin, a group, or a list of pins or groups. This configuration can include the + mux function to select on those pin(s)/group(s), and various pin configuration + parameters, such as pull-up, drive strength, etc. + + + PIN CONFIGURATION NODES: + + The name of each subnode is not important; all subnodes should be enumerated + and processed purely based on their content. + + Each subnode only affects those parameters that are explicitly listed. In + other words, a subnode that lists a mux function but no pin configuration + parameters implies no information about any pin configuration parameters. + Similarly, a pin subnode that describes a pullup parameter implies no + information about e.g. the mux function. + + + The following generic properties as defined in pinctrl-bindings.txt are valid + to specify in a pin configuration subnode: + + pins: + Usage: required + Value type: + Definition: List of gpio pins affected by the properties specified in + this subnode. + + Valid pins: + gpio0-gpio155 + Supports mux, bias and drive-strength + + sdc1_clk, sdc1_cmd, sdc1_data sdc2_clk, sdc2_cmd, + sdc2_data sdc1_rclk + Supports bias and drive-strength + + function: + Usage: required + Value type: + Definition: Specify the alternative function to be configured for the + specified pins. Functions are only valid for gpio pins. + Valid values: + blsp_uart1, blsp_spi1, blsp_i2c1, blsp_uim1, atest_tsens, + bimc_dte1, dac_calib0, blsp_spi8, blsp_uart8, blsp_uim8, + qdss_cti_trig_out_b, bimc_dte0, dac_calib1, qdss_cti_trig_in_b, + dac_calib2, atest_tsens2, atest_usb1, blsp_spi10, blsp_uart10, + blsp_uim10, atest_bbrx1, atest_usb13, atest_bbrx0, atest_usb12, + mdp_vsync, edp_lcd, blsp_i2c10, atest_gpsadc1, atest_usb11, + atest_gpsadc0, edp_hot, atest_usb10, m_voc, dac_gpio, atest_char, + cam_mclk, pll_bypassnl, qdss_stm7, blsp_i2c8, qdss_tracedata_b, + pll_reset, qdss_stm6, qdss_stm5, qdss_stm4, atest_usb2, cci_i2c, + qdss_stm3, dac_calib3, atest_usb23, atest_char3, dac_calib4, + qdss_stm2, atest_usb22, atest_char2, qdss_stm1, dac_calib5, + atest_usb21, atest_char1, dbg_out, qdss_stm0, dac_calib6, + atest_usb20, atest_char0, dac_calib10, qdss_stm10, + qdss_cti_trig_in_a, cci_timer4, blsp_spi6, blsp_uart6, blsp_uim6, + blsp2_spi, qdss_stm9, qdss_cti_trig_out_a, dac_calib11, + qdss_stm8, cci_timer0, qdss_stm13, dac_calib7, cci_timer1, + qdss_stm12, dac_calib8, cci_timer2, blsp1_spi, qdss_stm11, + dac_calib9, cci_timer3, cci_async, dac_calib12, blsp_i2c6, + qdss_tracectl_a, dac_calib13, qdss_traceclk_a, dac_calib14, + dac_calib15, hdmi_rcv, dac_calib16, hdmi_cec, pwr_modem, + dac_calib17, hdmi_ddc, pwr_nav, dac_calib18, pwr_crypto, + dac_calib19, hdmi_hot, dac_calib20, dac_calib21, pci_e0, + dac_calib22, dac_calib23, dac_calib24, tsif1_sync, dac_calib25, + sd_write, tsif1_error, blsp_spi2, blsp_uart2, blsp_uim2, + qdss_cti, blsp_i2c2, blsp_spi3, blsp_uart3, blsp_uim3, blsp_i2c3, + uim3, blsp_spi9, blsp_uart9, blsp_uim9, blsp10_spi, blsp_i2c9, + blsp_spi7, blsp_uart7, blsp_uim7, qdss_tracedata_a, blsp_i2c7, + qua_mi2s, gcc_gp1_clk_a, ssc_irq, uim4, blsp_spi11, blsp_uart11, + blsp_uim11, gcc_gp2_clk_a, gcc_gp3_clk_a, blsp_i2c11, cri_trng0, + cri_trng1, cri_trng, qdss_stm18, pri_mi2s, qdss_stm17, blsp_spi4, + blsp_uart4, blsp_uim4, qdss_stm16, qdss_stm15, blsp_i2c4, + qdss_stm14, dac_calib26, spkr_i2s, audio_ref, lpass_slimbus, + isense_dbg, tsense_pwm1, tsense_pwm2, btfm_slimbus, ter_mi2s, + qdss_stm22, qdss_stm21, qdss_stm20, qdss_stm19, gcc_gp1_clk_b, + sec_mi2s, blsp_spi5, blsp_uart5, blsp_uim5, gcc_gp2_clk_b, + gcc_gp3_clk_b, blsp_i2c5, blsp_spi12, blsp_uart12, blsp_uim12, + qdss_stm25, qdss_stm31, blsp_i2c12, qdss_stm30, qdss_stm29, + tsif1_clk, qdss_stm28, tsif1_en, tsif1_data, sdc4_cmd, qdss_stm27, + qdss_traceclk_b, tsif2_error, sdc43, vfr_1, qdss_stm26, tsif2_clk, + sdc4_clk, qdss_stm24, tsif2_en, sdc42, qdss_stm23, qdss_tracectl_b, + sd_card, tsif2_data, sdc41, tsif2_sync, sdc40, mdp_vsync_p_b, + ldo_en, mdp_vsync_s_b, ldo_update, blsp11_uart_tx_b, blsp11_uart_rx_b, + blsp11_i2c_sda_b, prng_rosc, blsp11_i2c_scl_b, uim2, uim1, uim_batt, + pci_e2, pa_indicator, adsp_ext, ddr_bist, qdss_tracedata_11, + qdss_tracedata_12, modem_tsync, nav_dr, nav_pps, pci_e1, gsm_tx, + qspi_cs, ssbi2, ssbi1, mss_lte, qspi_clk, qspi0, qspi1, qspi2, qspi3, + gpio + + bias-disable: + Usage: optional + Value type: + Definition: The specified pins should be configured as no pull. + + bias-pull-down: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull down. + + bias-pull-up: + Usage: optional + Value type: + Definition: The specified pins should be configured as pull up. + + output-high: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven high. + Not valid for sdc pins. + + output-low: + Usage: optional + Value type: + Definition: The specified pins are configured in output mode, driven low. + Not valid for sdc pins. + + drive-strength: + Usage: optional + Value type: + Definition: Selects the drive strength for the specified pins, in mA. + Valid values: 2, 4, 6, 8, 10, 12, 14 and 16 + +examples: + - | + tlmm: pinctrl@400000 { + compatible = "qcom,holi-pinctrl"; + reg = <0x400000 0x800000>; + interrupts = <0 227 0>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + };