From 4e63ed8ec1fb1d771900f191da74f5bd67ca7e57 Mon Sep 17 00:00:00 2001 From: "Vangala, Amarnath" Date: Fri, 28 Aug 2020 15:43:17 +0530 Subject: [PATCH] ARM: dts: msm: correction to adsp variant read entry Correction to the number of bits read for adsp variant identification. Include adsp_variant read entry for holi-atp variant. Update dtsi for ATP variant. Change-Id: I6b95d9f7b1e9a7196195b2e9cc29eae0567ba716 --- qcom/holi-atp-overlay.dts | 39 +++++++++++++++++++++++++++++++++++++++ qcom/holi-atp.dtsi | 1 + qcom/holi.dtsi | 2 +- 3 files changed, 41 insertions(+), 1 deletion(-) diff --git a/qcom/holi-atp-overlay.dts b/qcom/holi-atp-overlay.dts index a2d3433c..8062ff33 100644 --- a/qcom/holi-atp-overlay.dts +++ b/qcom/holi-atp-overlay.dts @@ -9,3 +9,42 @@ qcom,msm-id = <454 0x10000>, <472 0x10000>; qcom,board-id = <33 0>; }; + +&wsa881x_i2c_e { + status = "disabled"; +}; + +&wsa881x_i2c_44 { + status = "disabled"; +}; + +&wcd937x_tx_slave { + status = "disabled"; +}; + +&wcd937x_rx_slave { + status = "disabled"; +}; + +&wcd937x_codec { + status = "disabled"; +}; + +&holi_snd { + qcom,wcd-disabled = <1>; + qcom,audio-routing = + "RX_TX DEC0_INP", "TX DEC0 MUX", + "RX_TX DEC1_INP", "TX DEC1 MUX", + "RX_TX DEC2_INP", "TX DEC2 MUX", + "RX_TX DEC3_INP", "TX DEC3 MUX", + "VA SWR_INPUT", "VA_SWR_CLK", + "VA_AIF1 CAP", "VA_SWR_CLK", + "VA_AIF2 CAP", "VA_SWR_CLK", + "VA_AIF3 CAP", "VA_SWR_CLK", + "VA DMIC0", "Digital Mic0", + "VA DMIC1", "Digital Mic1", + "VA DMIC2", "Digital Mic2", + "VA DMIC3", "Digital Mic3", + "VA DMIC4", "Digital Mic4", + "VA DMIC5", "Digital Mic5"; +}; diff --git a/qcom/holi-atp.dtsi b/qcom/holi-atp.dtsi index ab7daf26..d6a7f551 100644 --- a/qcom/holi-atp.dtsi +++ b/qcom/holi-atp.dtsi @@ -1,3 +1,4 @@ +#include "holi-audio-overlay.dtsi" #include #include #include "holi-pmic-overlay.dtsi" diff --git a/qcom/holi.dtsi b/qcom/holi.dtsi index af27b19b..695e3ee6 100644 --- a/qcom/holi.dtsi +++ b/qcom/holi.dtsi @@ -2695,7 +2695,7 @@ adsp_variant: adsp_variant@1E6 { reg = <0x1E6 0x2>; - bits = <6 9>; + bits = <6 4>; }; feat_conf8: feat_conf8@6024 {