From ee05bcde63c4ade6a7e334ba0cd85a1384da692b Mon Sep 17 00:00:00 2001 From: Kalpak Kawadkar Date: Mon, 29 Aug 2022 16:23:11 +0530 Subject: [PATCH] ARM: dts: msm: Update the PCIE clocks support on NEO platforms PCIE clocks and GDSC's are not required to be controlled from HLOS on all NEO platforms. Hence add support for PCIE clocks and GDSC's only on specific platforms that require them. Change-Id: I94ddcd6bc3954d4da0dbcaa9ce566399deb4c9d7 --- qcom/neo-idp-mos.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ qcom/neo-qxr-mos.dtsi | 42 ++++++++++++++++++++++++++++++++++++++++++ qcom/neo.dtsi | 41 +++++++++++++++++++++++++++-------------- qcom/neo_la.dtsi | 39 --------------------------------------- 4 files changed, 110 insertions(+), 53 deletions(-) diff --git a/qcom/neo-idp-mos.dtsi b/qcom/neo-idp-mos.dtsi index f9e058d5..7e1d6265 100644 --- a/qcom/neo-idp-mos.dtsi +++ b/qcom/neo-idp-mos.dtsi @@ -1,5 +1,46 @@ #include "neo-idp.dtsi" +#include +#include &soc { }; +&tcsrcc { + protected-clocks = , + ; +}; + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + protected-clocks = , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + ; +}; + +&gcc_pcie_0_gdsc { + status = "disabled"; +}; + +&gcc_pcie_0_phy_gdsc { + status = "disabled"; +}; + +&gcc_pcie_1_gdsc { + status = "disabled"; +}; + +&gcc_pcie_1_phy_gdsc { + status = "disabled"; +}; diff --git a/qcom/neo-qxr-mos.dtsi b/qcom/neo-qxr-mos.dtsi index 60bd75f0..40b751d9 100644 --- a/qcom/neo-qxr-mos.dtsi +++ b/qcom/neo-qxr-mos.dtsi @@ -1,4 +1,46 @@ #include "neo-qxr.dtsi" +#include +#include &soc { }; + +&tcsrcc { + protected-clocks = , + ; +}; + +&gcc { + clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; + clock-names = "bi_tcxo", "sleep_clk", + "usb3_phy_wrapper_gcc_usb30_pipe_clk"; + protected-clocks = , + , , + , , + , , + , , + , , + , , + , , + , , + , , + , , + ; +}; + +&gcc_pcie_0_gdsc { + status = "disabled"; +}; + +&gcc_pcie_0_phy_gdsc { + status = "disabled"; +}; + +&gcc_pcie_1_gdsc { + status = "disabled"; +}; + +&gcc_pcie_1_phy_gdsc { + status = "disabled"; +}; diff --git a/qcom/neo.dtsi b/qcom/neo.dtsi index 78d33e7b..257f1957 100644 --- a/qcom/neo.dtsi +++ b/qcom/neo.dtsi @@ -728,21 +728,11 @@ vdd_cx-supply = <&VDD_CX_LEVEL>; vdd_mxa-supply = <&VDD_MXA_LEVEL>; clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, + <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; clock-names = "bi_tcxo", "sleep_clk", + "pcie_0_pipe_clk", "pcie_1_pipe_clk", "usb3_phy_wrapper_gcc_usb30_pipe_clk"; - protected-clocks = , - , , - , , - , , - , , - , , - , , - , , - , , - , , - , , - ; #clock-cells = <1>; #reset-cells = <1>; }; @@ -831,8 +821,6 @@ compatible = "qcom,tcsrcc", "syscon"; reg = <0x1fc0000 0x30000>; reg-name = "cc_base"; - protected-clocks = , - ; #clock-cells = <1>; #reset-cells = <1>; }; @@ -2399,6 +2387,31 @@ status = "ok"; }; +&gcc_pcie_0_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; + /delete-property/ qcom,support-hw-trigger; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 0>; +}; + +&gcc_pcie_0_phy_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 3>; +}; + +&gcc_pcie_1_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 1>; +}; + +&gcc_pcie_1_phy_gdsc { + parent-supply = <&VDD_CX_LEVEL>; + status = "ok"; + qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 4>; +}; + &cam_cc_bps_gdsc { clocks = <&gcc GCC_CAMERA_AHB_CLK>; clock-names = "ahb_clk"; diff --git a/qcom/neo_la.dtsi b/qcom/neo_la.dtsi index d11b8904..e022afa8 100644 --- a/qcom/neo_la.dtsi +++ b/qcom/neo_la.dtsi @@ -70,45 +70,6 @@ }; }; -&tcsrcc { - /delete-property/ protected-clocks; -}; - -&gcc { - clocks = <&rpmhcc RPMH_CXO_CLK>, <&sleep_clk>, - <&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>, - <&usb3_phy_wrapper_gcc_usb30_pipe_clk>; - clock-names = "bi_tcxo", "sleep_clk", - "pcie_0_pipe_clk", "pcie_1_pipe_clk", - "usb3_phy_wrapper_gcc_usb30_pipe_clk"; - /delete-property/ protected-clocks; -}; - -&gcc_pcie_0_gdsc { - parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; - /delete-property/ qcom,support-hw-trigger; - qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 0>; -}; - -&gcc_pcie_0_phy_gdsc { - parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; - qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 3>; -}; - -&gcc_pcie_1_gdsc { - parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; - qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 1>; -}; - -&gcc_pcie_1_phy_gdsc { - parent-supply = <&VDD_CX_LEVEL>; - status = "ok"; - qcom,collapse-vote = <&gcc_apcs_gdsc_vote_ctrl &gcc_apcs_gdsc_sleep_ctrl 4>; -}; - &wpss_pas { status = "disabled"; /delete-property/ memory-region;