From 22e595cc91ec5bd7dc943b48b160f043f4bdbe56 Mon Sep 17 00:00:00 2001 From: Zhenhua Huang Date: Wed, 21 Sep 2022 18:10:14 +0800 Subject: [PATCH] ARM: dts: msm: Enable gfx smmu and config clks Enable gfx smmu, also config clks needed. Change-Id: I6d0e27294d8f7533b77f173845c2f1841077c117 --- qcom/msm-arm-smmu-ravelin.dtsi | 18 +++++++++++++++++- 1 file changed, 17 insertions(+), 1 deletion(-) diff --git a/qcom/msm-arm-smmu-ravelin.dtsi b/qcom/msm-arm-smmu-ravelin.dtsi index 05c45522..db279829 100644 --- a/qcom/msm-arm-smmu-ravelin.dtsi +++ b/qcom/msm-arm-smmu-ravelin.dtsi @@ -10,17 +10,33 @@ qcom,use-3-lvl-tables; qcom,num-context-banks-override = <0x5>; qcom,num-smr-override = <0x7>; - status = "disabled"; #global-interrupts = <1>; #size-cells = <1>; #address-cells = <1>; ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x0 0x1FFF 0x328>; + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = + "gpu_cc_cx_gmu", + "gpu_cc_hub_cx_int", + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + interrupts = , , ,