From be31f23131fe780f96ab31648582c30294616367 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 28 Oct 2022 15:32:18 +0530 Subject: [PATCH 1/4] ARM: dts: msm: Add interconnects and interrupt to Ravelin Added interconnects for usb_ddr, ddr_ipa & ddr_usb access, interrupts dp,dm,ss_phy_irq for Ravelin. Change-Id: I340168068192acfdce7bcb55746d339659702a6a --- qcom/ravelin-usb.dtsi | 23 +++++++++++++++++++++-- 1 file changed, 21 insertions(+), 2 deletions(-) diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index cf9fb16e..3e78de27 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -22,12 +22,31 @@ resets = <&gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; - interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>; - interrupt-names = "pwr_event_irq"; + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_RISING>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_RISING>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; qcom,core-clk-rate = <133333333>; qcom,core-clk-rate-hs = <66666667>; + qcom,pm-qos-latency = <2>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + + interconnect-names = "usb-ddr", "usb-ipa", "ddr-usb"; + interconnects = <&aggre2_noc MASTER_USB3_0 &mc_virt SLAVE_EBI1>, + <&aggre2_noc MASTER_USB3_0 &cnoc2 SLAVE_IPA_CFG>, + <&gem_noc MASTER_APPSS_PROC &cnoc2 SLAVE_USB3_0>; dwc3@a600000 { compatible = "snps,dwc3"; From 4c41cf4d020e2fc7e4cc77b4847e46576e440c6c Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 28 Oct 2022 16:38:16 +0530 Subject: [PATCH 2/4] ARM: dts: msm: Add HS USB PHY support in Ravelin Add HS USB PHY node in ravelin usb in order to support device detection in HS mode. Change-Id: If79a1dcd4a9425837988ada2643b4185102617ac --- qcom/ravelin-rumi.dtsi | 4 ---- qcom/ravelin-usb.dtsi | 29 +++++++++++++++++++++++++++-- 2 files changed, 27 insertions(+), 6 deletions(-) diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi index 4cd9043a..0599abd2 100644 --- a/qcom/ravelin-rumi.dtsi +++ b/qcom/ravelin-rumi.dtsi @@ -14,10 +14,6 @@ status = "disabled"; }; - usb_nop_phy: usb_nop_phy { - compatible = "usb-nop-xceiv"; - }; - usb_emuphy: phy@a784000 { compatible = "qcom,usb-emu-phy"; reg = <0x0a784000 0x9500>; diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index 3e78de27..482b8bdc 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -58,17 +58,42 @@ dma-coherent; interrupts = ; - snps,disable-clk-gating; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; tx-fifo-resize; dr_mode = "otg"; - maximum-speed = "super-speed"; + maximum-speed = "high-speed"; }; }; + /* USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x11c>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L5B>; + vdda18-supply = <&L23B>; + vdda33-supply = <&L25B>; + qcom,vdd-voltage-level = <0 880000 920000>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; + }; From be015c9c4112ece1634c3e86936f9953c04b5081 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 4 Nov 2022 15:09:43 +0530 Subject: [PATCH 3/4] ARM: dts: msm: Add QMP PHY node for Ravelin Add QMP DP Combo Phy node for Ravelin. Change-Id: Id055546a44797cd20ec3c8f5e83e7009446e4739 --- qcom/ravelin-usb.dtsi | 209 +++++++++++++++++++++++++++++++++++++++++- 1 file changed, 207 insertions(+), 2 deletions(-) diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index 482b8bdc..dda8fe99 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { usb0: ssusb@a600000 { @@ -58,7 +59,7 @@ dma-coherent; interrupts = ; - usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; @@ -68,7 +69,7 @@ snps,dis_u3_susphy_quirk; tx-fifo-resize; dr_mode = "otg"; - maximum-speed = "high-speed"; + maximum-speed = "super-speed"; }; }; @@ -96,4 +97,208 @@ compatible = "usb-nop-xceiv"; }; + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e8000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e8000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L7B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L16B>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; + + usb_audio_qmi_dev { + compatible = "qcom,usb-audio-qmi-dev"; + iommus = <&apps_smmu 0x180f 0x0>; + qcom,iommu-dma = "disabled"; + qcom,usb-audio-stream-id = <0xf>; + qcom,usb-audio-intr-num = <2>; + }; + }; From 6e6adb308e5f0093c2ec3b9a05f45f775802ff5e Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Fri, 4 Nov 2022 16:37:56 +0530 Subject: [PATCH 4/4] ARM: dts: msm: Add ref_clk to PHY node for Ravelin This change adds proper ref_clk for PHY to be operational on Ravelin. Change-Id: Ib6078129a5bfdeac2f7abbf3a5251525ceb88fa2 --- qcom/ravelin-usb.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi index dda8fe99..f1230875 100644 --- a/qcom/ravelin-usb.dtsi +++ b/qcom/ravelin-usb.dtsi @@ -86,8 +86,9 @@ vdda33-supply = <&L25B>; qcom,vdd-voltage-level = <0 880000 920000>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_EUSB3_0_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; @@ -113,10 +114,11 @@ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_0_CLKREF_EN>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", - "com_aux_clk"; + "com_aux_clk", "ref_clk"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>;