diff --git a/qcom/shima-thermal.dtsi b/qcom/shima-thermal.dtsi index 6741751d..bb3fb6bc 100644 --- a/qcom/shima-thermal.dtsi +++ b/qcom/shima-thermal.dtsi @@ -1,4 +1,66 @@ #include +#include "lahaina-thermal-modem.dtsi" + +&qmi_tmd { + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; +}; + +&cpufreq_hw { + qcom,cpu-isolation { + compatible = "qcom,cpu-isolate"; + cpu0_isolate: cpu0-isolate { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_isolate: cpu1-isolate { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_isolate: cpu2-isolate { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_isolate: cpu3-isolate { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + + cpu4_isolate: cpu4-isolate { + qcom,cpu = <&CPU4>; + #cooling-cells = <2>; + }; + + cpu5_isolate: cpu5-isolate { + qcom,cpu = <&CPU5>; + #cooling-cells = <2>; + }; + + cpu6_isolate: cpu6-isolate { + qcom,cpu = <&CPU6>; + #cooling-cells = <2>; + }; + + cpu7_isolate: cpu7-isolate { + qcom,cpu = <&CPU7>; + #cooling-cells = <2>; + }; + }; +}; &thermal_zones { aoss-0-usr { @@ -580,5 +642,401 @@ }; }; }; + + nspss-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 3>; + thermal-governor = "step_wise"; + trips { + nspss0_trip0: nspss0-trip0 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&nspss0_trip0>; + cooling-device = <&cdsp_sw 3 3>; + }; + + modem-pa-cdev { + trip = <&nspss0_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&nspss0_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + nspss-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 4>; + thermal-governor = "step_wise"; + trips { + nspss1_trip0: nspss1-trip0 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&nspss1_trip0>; + cooling-device = <&cdsp_sw 3 3>; + }; + + modem-pa-cdev { + trip = <&nspss1_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&nspss1_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + nspss-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens1 5>; + thermal-governor = "step_wise"; + trips { + nspss2_trip0: nspss2-trip0 { + temperature = <100000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + cdsp-cdev { + trip = <&nspss2_trip0>; + cooling-device = <&cdsp_sw 3 3>; + }; + + modem-pa-cdev { + trip = <&nspss2_trip0>; + cooling-device = <&modem_pa 3 3>; + }; + + modem-tj-cdev { + trip = <&nspss2_trip0>; + cooling-device = <&modem_tj 3 3>; + }; + }; + }; + + cpu-0-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 1>; + trips { + cpu00_config: cpu00-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu00_cdev { + trip = <&cpu00_config>; + cooling-device = <&cpu0_isolate 1 1>; + }; + }; + }; + + cpu-0-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 2>; + trips { + cpu01_config: cpu01-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu01_config>; + cooling-device = <&cpu1_isolate 1 1>; + }; + }; + }; + + cpu-0-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens0 3>; + trips { + cpu02_config: cpu02-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu02_config>; + cooling-device = <&cpu2_isolate 1 1>; + }; + }; + }; + + cpu-0-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 4>; + thermal-governor = "step_wise"; + trips { + cpu03_config: cpu03-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu03_config>; + cooling-device = <&cpu3_isolate 1 1>; + }; + }; + }; + + cpu-1-0-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 7>; + thermal-governor = "step_wise"; + trips { + cpu10_config: cpu10-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu10_cdev { + trip = <&cpu10_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu10_cdev1 { + trip = <&cpu10_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-1-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 8>; + thermal-governor = "step_wise"; + trips { + cpu11_config: cpu11-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu11_cdev { + trip = <&cpu11_config>; + cooling-device = <&cpu4_isolate 1 1>; + }; + + cpu11_cdev1 { + trip = <&cpu11_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-2-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 9>; + thermal-governor = "step_wise"; + trips { + cpu12_config: cpu12-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu12_cdev { + trip = <&cpu12_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu12_cdev1 { + trip = <&cpu12_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-3-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 10>; + thermal-governor = "step_wise"; + trips { + cpu13_config: cpu13-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu13_cdev { + trip = <&cpu13_config>; + cooling-device = <&cpu5_isolate 1 1>; + }; + + cpu13_cdev1 { + trip = <&cpu13_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-4-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 11>; + thermal-governor = "step_wise"; + trips { + cpu14_config: cpu14-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu14_cdev { + trip = <&cpu14_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu14_cdev1 { + trip = <&cpu14_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-5-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 12>; + thermal-governor = "step_wise"; + trips { + cpu15_config: cpu15-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu15_cdev { + trip = <&cpu15_config>; + cooling-device = <&cpu6_isolate 1 1>; + }; + + cpu15_cdev1 { + trip = <&cpu15_config>; + cooling-device = <&CPU4 THERMAL_MAX_LIMIT + THERMAL_MAX_LIMIT>; + }; + }; + }; + + cpu-1-6-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 13>; + thermal-governor = "step_wise"; + trips { + cpu16_config: cpu16-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu16_cdev { + trip = <&cpu16_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + cpu-1-7-step { + polling-delay-passive = <0>; + polling-delay = <0>; + thermal-sensors = <&tsens0 14>; + thermal-governor = "step_wise"; + trips { + cpu17_config: cpu17-config { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu17_cdev { + trip = <&cpu17_config>; + cooling-device = <&cpu7_isolate 1 1>; + }; + }; + }; + + gpuss-max-step { + polling-delay-passive = <10>; + polling-delay = <100>; + thermal-governor = "step_wise"; + thermal-sensors = <&tsens1 1>, <&tsens1 2>; + sensor-aggregation = ; + trips { + gpuss_config: active-config0 { + temperature = <95000>; + hysteresis = <20000>; + type = "passive"; + }; + }; + }; }; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index c26092c8..85ff0d13 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -41,6 +41,7 @@ dynamic-power-coefficient = <100>; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_0>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -63,6 +64,7 @@ dynamic-power-coefficient = <100>; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_1>; + #cooling-cells = <2>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -80,6 +82,7 @@ dynamic-power-coefficient = <100>; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_2>; + #cooling-cells = <2>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -97,6 +100,7 @@ dynamic-power-coefficient = <100>; cpu-idle-states = <&SLVR_OFF &SLVR_RAIL_OFF>; next-level-cache = <&L2_3>; + #cooling-cells = <2>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -114,6 +118,7 @@ dynamic-power-coefficient = <520>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_4>; + #cooling-cells = <2>; L2_4: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -131,6 +136,7 @@ dynamic-power-coefficient = <520>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_5>; + #cooling-cells = <2>; L2_5: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -148,6 +154,7 @@ dynamic-power-coefficient = <520>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_6>; + #cooling-cells = <2>; L2_6: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -165,6 +172,7 @@ dynamic-power-coefficient = <552>; cpu-idle-states = <&GOLD_OFF &GOLD_RAIL_OFF>; next-level-cache = <&L2_7>; + #cooling-cells = <2>; L2_7: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -1387,6 +1395,10 @@ thermal_zones: thermal-zones { }; + qmi_tmd: qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + }; + tsens0:tsens@c222000 { compatible = "qcom,tsens24xx"; reg = <0x0C222000 0x8>,