From 4cac88622ed6206bf591bee86d68481735186b88 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 24 May 2022 17:16:08 +0530 Subject: [PATCH 1/3] ARM: dts: msm: Add HS USB PHY support in Anorak Added HS USB Phy node in Anorak in order to support device detection in HS mode. Change-Id: I471f8f73dd0f53384b35e86da6cffe9fa4a872f5 --- qcom/anorak-rumi.dtsi | 4 ---- qcom/anorak-usb.dtsi | 30 +++++++++++++++++++++++++++--- 2 files changed, 27 insertions(+), 7 deletions(-) diff --git a/qcom/anorak-rumi.dtsi b/qcom/anorak-rumi.dtsi index 1551d2b3..106004dc 100644 --- a/qcom/anorak-rumi.dtsi +++ b/qcom/anorak-rumi.dtsi @@ -9,10 +9,6 @@ }; &soc { - usb_nop_phy: usb_nop_phy { - compatible = "usb-nop-xceiv"; - }; - usb_emuphy: phy@a784000 { compatible = "qcom,usb-emu-phy"; reg = <0x0a784000 0x9500>; diff --git a/qcom/anorak-usb.dtsi b/qcom/anorak-usb.dtsi index 9953ac6d..4ce45135 100644 --- a/qcom/anorak-usb.dtsi +++ b/qcom/anorak-usb.dtsi @@ -51,17 +51,41 @@ dma-coherent; interrupts = ; - - snps,disable-clk-gating; + usb-phy = <&usb2_phy0>, <&usb_nop_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; snps,dis-u1-entry-quirk; snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; + snps,dis_u3_susphy_quirk; tx-fifo-resize; dr_mode = "otg"; - maximum-speed = "super-speed-plus"; + maximum-speed = "high-speed"; }; }; + + /* USB port related High Speed PHY */ + usb2_phy0: hsphy@88e3000 { + compatible = "qcom,usb-hsphy-snps-femto"; + reg = <0x88e3000 0x11c>, + <0x088e2000 0x4>; + reg-names = "hsusb_phy_base", + "eud_enable_reg"; + + vdd-supply = <&L1D>; + vdda18-supply = <&L10B>; + vdda33-supply = <&L15B>; + qcom,vdd-voltage-level = <0 880000 918750>; + + clocks = <&rpmhcc RPMH_CXO_CLK>; + clock-names = "ref_clk_src"; + + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; + reset-names = "phy_reset"; + }; + + usb_nop_phy: usb_nop_phy { + compatible = "usb-nop-xceiv"; + }; }; From c5089358c1541d54c00edc0c9814773abdcb9f39 Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Tue, 31 May 2022 19:22:12 +0530 Subject: [PATCH 2/3] ARM: dts: msm: Add QMP PHY node for Anorak Add QMP DP Combo Phy node for Anorak. Change-Id: Idfb1e28c30f3075423fb35784c5651f3f70e5a52 --- qcom/anorak-usb.dtsi | 204 ++++++++++++++++++++++++++++++++++++++++++- 1 file changed, 202 insertions(+), 2 deletions(-) diff --git a/qcom/anorak-usb.dtsi b/qcom/anorak-usb.dtsi index 4ce45135..0e8a7f5e 100644 --- a/qcom/anorak-usb.dtsi +++ b/qcom/anorak-usb.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { usb0: ssusb@a600000 { @@ -51,7 +52,7 @@ dma-coherent; interrupts = ; - usb-phy = <&usb2_phy0>, <&usb_nop_phy>; + usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x0>; snps,is-utmi-l1-suspend; @@ -61,7 +62,7 @@ snps,dis_u3_susphy_quirk; tx-fifo-resize; dr_mode = "otg"; - maximum-speed = "high-speed"; + maximum-speed = "super-speed-plus"; }; }; @@ -88,4 +89,203 @@ usb_nop_phy: usb_nop_phy { compatible = "usb-nop-xceiv"; }; + + /* USB port related QMP USB DP Combo PHY */ + usb_qmp_dp_phy: ssphy@88e6000 { + compatible = "qcom,usb-ssphy-qmp-dp-combo"; + reg = <0x88e6000 0x3000>; + reg-names = "qmp_phy_base"; + + vdd-supply = <&L1B>; + qcom,vdd-voltage-level = <0 912000 912000>; + qcom,vdd-max-load-uA = <47000>; + core-supply = <&L2C>; + + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>, + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, + <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", + "pipe_clk_ext_src", "ref_clk_src", + "com_aux_clk"; + + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, + <&gcc GCC_USB3_PHY_PRIM_BCR>; + reset-names = "global_phy_reset", "phy_reset"; + + pinctrl-names = "default"; + pinctrl-0 = <&usb3phy_portselect_default>; + + qcom,qmp-phy-reg-offset = + ; + + qcom,qmp-phy-init-seq = + /* */ + ; + }; }; From 310c5c6abe5d45b8434e32922d1de2aab20cb6fb Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 14 Jul 2022 18:40:56 +0530 Subject: [PATCH 3/3] ARM: dts: msm: Add ref_clk to PHY node for Anorak This change adds proper ref_clk for PHY to be operational on Anorak. Change-Id: I6a7e72027f9ff49ad2e6091a0146d6a16fa8b6f6 --- qcom/anorak-usb.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/qcom/anorak-usb.dtsi b/qcom/anorak-usb.dtsi index 0e8a7f5e..fd19fb72 100644 --- a/qcom/anorak-usb.dtsi +++ b/qcom/anorak-usb.dtsi @@ -79,8 +79,9 @@ vdda33-supply = <&L15B>; qcom,vdd-voltage-level = <0 880000 918750>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB2_0_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; @@ -106,10 +107,11 @@ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_0_CLKREF_EN>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", - "com_aux_clk"; + "com_aux_clk", "ref_clk"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>;