From 2999b44d3927ccb95d1eedea449936bf9aa83ce8 Mon Sep 17 00:00:00 2001
From: Prateek Sood <prsood@qti.qualcomm.com>
Date: Wed, 20 Jan 2021 14:56:17 +0530
Subject: [PATCH] ARM: dts: msm: Add pinctrl node for TLMM on Diwali SoC

Add pinctrl node with compatiability of qcom,diwali-pinctrl,
to enable Top Level Mode Multiplexer block(TLMM) on Diwali SoC.

Change-Id: Iebbfeb7c0d4729070b4716e2ccdafc52ed5a21e6
---
 qcom/diwali-pinctrl.dtsi |  1 +
 qcom/diwali.dtsi         | 12 ++++++++++++
 2 files changed, 13 insertions(+)
 create mode 100644 qcom/diwali-pinctrl.dtsi

diff --git a/qcom/diwali-pinctrl.dtsi b/qcom/diwali-pinctrl.dtsi
new file mode 100644
index 00000000..8b7b9bd9
--- /dev/null
+++ b/qcom/diwali-pinctrl.dtsi
@@ -0,0 +1 @@
+&tlmm { };
diff --git a/qcom/diwali.dtsi b/qcom/diwali.dtsi
index 4f5b6afe..fbae70c5 100644
--- a/qcom/diwali.dtsi
+++ b/qcom/diwali.dtsi
@@ -189,6 +189,16 @@
 		interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>;
 	};
 
+	tlmm: pinctrl@f000000 {
+		compatible = "qcom,diwali-pinctrl";
+		reg = <0x0F000000 0x1000000>;
+		interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>;
+		gpio-controller;
+		#gpio-cells = <2>;
+		interrupt-controller;
+		#interrupt-cells = <2>;
+	};
+
 	wdog: qcom,wdt@17410000 {
 		compatible = "qcom,msm-watchdog";
 		reg = <0x17410000 0x1000>;
@@ -264,3 +274,5 @@
 		};
 	};
 };
+
+#include "diwali-pinctrl.dtsi"