From ca52a2a00b389cf51f478eb5d620dacf65bb0dd9 Mon Sep 17 00:00:00 2001
From: Yuanfang Zhang <yuanfang@qti.qualcomm.com>
Date: Mon, 20 Dec 2021 16:38:37 +0800
Subject: [PATCH] ARM: dts: msm: add dl_lpass_cti on diwali

Add QDSS_DL_LPASSCTI0_CTI0_QC_CTI_CORE CTI on diwali.

Change-Id: I545959763abdb3c9afdacccc53f624c1a43d994e
---
 qcom/diwali-coresight.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)

diff --git a/qcom/diwali-coresight.dtsi b/qcom/diwali-coresight.dtsi
index 52eaa4bf..2ab1cdc1 100644
--- a/qcom/diwali-coresight.dtsi
+++ b/qcom/diwali-coresight.dtsi
@@ -3239,6 +3239,17 @@
 		clock-names = "apb_pclk";
 	};
 
+	dl_lpass_cti: cti@10c4a000  {
+		compatible = "arm,coresight-cti", "arm,primecell";
+		reg = <0x10c4a000  0x1000>;
+
+		arm,primecell-periphid = <0x000bb922>;
+		coresight-name = "coresight-cti-dl_lpass_cti";
+
+		clocks = <&aoss_qmp>;
+		clock-names = "apb_pclk";
+	};
+
 	gpu_isdb_cti: cti@10961000 {
 		compatible = "arm,coresight-cti", "arm,primecell";
 		reg = <0x10961000 0x1000>;