diff --git a/qcom/mmrm/Kbuild b/qcom/mmrm/Kbuild
new file mode 100644
index 00000000..ea13e2ef
--- /dev/null
+++ b/qcom/mmrm/Kbuild
@@ -0,0 +1,23 @@
+ifeq ($(CONFIG_ARCH_WAIPIO), y)
+dtbo-y += waipio-mmrm.dtbo
+dtbo-y += waipio-mmrm-test.dtbo
+dtbo-y += waipio-v2-mmrm.dtbo
+dtbo-y += waipio-v2-mmrm-test.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_NEO), y)
+dtbo-y += neo-mmrm.dtbo
+dtbo-y += neo-mmrm-test.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_CAPE), y)
+dtbo-y += cape-mmrm.dtbo
+endif
+
+ifeq ($(CONFIG_ARCH_DIWALI), y)
+dtbo-y += diwali-mmrm.dtbo
+endif
+
+always-y	:= $(dtb-y) $(dtbo-y)
+subdir-y	:= $(dts-dirs)
+clean-files	:= *.dtb *.dtbo
diff --git a/qcom/mmrm/Makefile b/qcom/mmrm/Makefile
new file mode 100644
index 00000000..b1e0dfe9
--- /dev/null
+++ b/qcom/mmrm/Makefile
@@ -0,0 +1,9 @@
+KBUILD_OPTIONS+=KBUILD_EXTMOD_DTS=.
+
+all: dtbs
+
+clean:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) clean
+
+%:
+	$(MAKE) -C $(KERNEL_SRC) M=$(M) $@ $(KBUILD_OPTIONS)
diff --git a/qcom/mmrm/bindings/msm-mmrm-test.txt b/qcom/mmrm/bindings/msm-mmrm-test.txt
new file mode 100644
index 00000000..b85b5846
--- /dev/null
+++ b/qcom/mmrm/bindings/msm-mmrm-test.txt
@@ -0,0 +1,32 @@
+* Qualcomm Technologies, Inc. MSM MMRM
+
+[Root level node]
+MMRM
+=====
+Required properties:
+- compatible : one of:
+	- "qcom,msm-mmrm-test"
+	- "qcom,waipio-mmrm-test" : Invokes driver specific data for Waipio.
+- clock-names: an array of clocks that the driver uses for testing.
+	The clocks names here correspond to the clock names used in
+	clk_get.
+- clocks: Must contain an entry for each clock in clock-names.
+
+Example:
+
+	qcom,mmrm-test {
+		compatible = "qcom,msm-mmrm-test";
+
+		clock-names =
+			"cam_cc_ife_0_clk_src",
+			"cam_cc_ife_1_clk_src",
+			"video_cc_mvs1_clk_src",
+			"disp_cc_mdss_mdp_clk_src",
+			"video_cc_mvs0_clk_src";
+		clocks =
+			<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+			<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
+			<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
+	};
diff --git a/qcom/mmrm/bindings/msm-mmrm.txt b/qcom/mmrm/bindings/msm-mmrm.txt
new file mode 100644
index 00000000..9019bc5c
--- /dev/null
+++ b/qcom/mmrm/bindings/msm-mmrm.txt
@@ -0,0 +1,35 @@
+* Qualcomm Technologies, Inc. MSM MMRM
+
+[Root level node]
+MMRM
+=====
+Required properties:
+- compatible : one of:
+	- "qcom,msm-mmrm"
+	- "qcom,waipio-mmrm" : Invokes driver specific data for Waipio.
+Optional properties:
+- mm-rail-corners : an array of voltage corner names supported by driver.
+- mm-rail-fact-volt : an array of voltage coner factors corresponding to
+  voltage corners supported by driver for a chipset.
+- scaling-fact-dyn : an array of dynamic scaling factors corresponding to
+  voltage corners supported by driver for a chipset.
+- scaling-fact-leak: an array of leakage scaling factors corresponding to
+  voltage corners supported by driver for a chipset.
+- client-info : an array of information for each clock source. Each entry
+  includes client domain, clk src id & corresponding power factors.
+
+Example:
+
+	qcom,mmrm {
+		compatible = "qcom,msm-mmrm";
+
+		mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
+		mm-rail-fact-volt = <36439 41157 44827 49152 54526>;
+
+		/* Scaling factors */
+		scaling-fact-dyn = <35390 45876 54395 66192 82576>;
+		scaling-fact-leak = <451544 548537 633078 746456 920126>;
+
+		client-info =
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582288>;
+	};
diff --git a/qcom/mmrm/cape-mmrm.dts b/qcom/mmrm/cape-mmrm.dts
new file mode 100644
index 00000000..c1bfb5f0
--- /dev/null
+++ b/qcom/mmrm/cape-mmrm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-waipio.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+#include <dt-bindings/clock/qcom,dispcc-waipio.h>
+#include "cape-mmrm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Cape/Ukee SoC";
+	compatible = "qcom,cape", "qcom,ukee";
+	qcom,msm-id = <530 0x10000>, <531 0x10000>, <540 0x10000>, <591 0x10000>;
+	qcom,board-id = <0 0>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/cape-mmrm.dtsi b/qcom/mmrm/cape-mmrm.dtsi
new file mode 100644
index 00000000..f06601c4
--- /dev/null
+++ b/qcom/mmrm/cape-mmrm.dtsi
@@ -0,0 +1,46 @@
+&soc {
+	msm_mmrm: qcom,mmrm {
+		compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm";
+		status = "okay";
+
+		/* MM Rail info */
+		mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
+		mm-rail-fact-volt = <37487 41157 44827 47711 52429>;
+
+		/* Scaling factors */
+		scaling-fact-dyn = <39951 48654 58347 66677 81757>;
+		scaling-fact-leak = <39951 671797 784172 884468 1082937>;
+
+		/* Client info */
+		mmrm-client-info =
+			<0x1 CAM_CC_IFE_0_CLK_SRC 28892522 209716 1>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 28892522 209716 1>,
+			<0x1 CAM_CC_IFE_2_CLK_SRC 28892522 209716 1>,
+			<0x1 CAM_CC_CSID_CLK_SRC 1858221 0 3>,
+			<0x1 CAM_CC_SFE_0_CLK_SRC 16591281 116327 1>,
+			<0x1 CAM_CC_SFE_1_CLK_SRC 16591281 116327 1>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 57984156 481100 1>,
+			<0x1 CAM_CC_BPS_CLK_SRC 17057081 132645 1>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 1460798 19006 5>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 870214 0 2>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 2930770 454165 1>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 225444 0 5>,
+			<0x1 CAM_CC_ICP_CLK_SRC 270533 0 1>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 191628 0 9>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 564 0 1>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 564 0 1>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 60307 0 1>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 30435 0 1>,
+
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 62980096 343409 1>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 18345493 251659 1>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 912917 5243 1>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 36275487 475792 1>;
+	};
+};
diff --git a/qcom/mmrm/diwali-mmrm.dts b/qcom/mmrm/diwali-mmrm.dts
new file mode 100644
index 00000000..722f9fd7
--- /dev/null
+++ b/qcom/mmrm/diwali-mmrm.dts
@@ -0,0 +1,11 @@
+/dts-v1/;
+/plugin/;
+
+#include "diwali-mmrm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. diwali SoC";
+	compatible = "qcom,diwali";
+	qcom,msm-id = <506 0x10000>;
+	qcom,board-id = <0 0>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/diwali-mmrm.dtsi b/qcom/mmrm/diwali-mmrm.dtsi
new file mode 100644
index 00000000..145b19bf
--- /dev/null
+++ b/qcom/mmrm/diwali-mmrm.dtsi
@@ -0,0 +1,6 @@
+&soc {
+	msm_mmrm: qcom,mmrm {
+		compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm";
+		status = "okay";
+	};
+};
diff --git a/qcom/mmrm/neo-mmrm-test.dts b/qcom/mmrm/neo-mmrm-test.dts
new file mode 100644
index 00000000..fdac31e1
--- /dev/null
+++ b/qcom/mmrm/neo-mmrm-test.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-neo.h>
+#include <dt-bindings/clock/qcom,videocc-neo.h>
+#include <dt-bindings/clock/qcom,dispcc-neo.h>
+#include "neo-mmrm-test.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Neo v1 SoC";
+	compatible = "qcom,neo";
+	qcom,msm-id = <554 0x10000>;
+	qcom,board-id = <34 1>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/neo-mmrm-test.dtsi b/qcom/mmrm/neo-mmrm-test.dtsi
new file mode 100644
index 00000000..76d43361
--- /dev/null
+++ b/qcom/mmrm/neo-mmrm-test.dtsi
@@ -0,0 +1,81 @@
+&soc {
+	msm_mmrm_test: qcom,mmrm-test {
+		compatible = "qcom,msm-mmrm-test", "qcom,neo-mmrm-test";
+		status = "disable";
+
+		/* Clock info */
+		clock-names =
+			"cam_cc_ife_0_clk_src",
+			"cam_cc_ife_1_clk_src",
+			"cam_cc_csid_clk_src",
+			"cam_cc_ipe_nps_clk_src",
+			"cam_cc_bps_clk_src",
+			"cam_cc_ife_lite_clk_src",
+			"cam_cc_jpeg_clk_src",
+			"cam_cc_camnoc_axi_clk_src",
+			"cam_cc_ife_lite_csid_clk_src",
+			"cam_cc_icp_clk_src",
+			"cam_cc_cphy_rx_clk_src",
+			"cam_cc_csi0phytimer_clk_src",
+			"cam_cc_csi1phytimer_clk_src",
+			"cam_cc_csi2phytimer_clk_src",
+			"cam_cc_csi3phytimer_clk_src",
+			"cam_cc_cci_0_clk_src",
+			"cam_cc_cci_1_clk_src",
+			"cam_cc_slow_ahb_clk_src",
+			"cam_cc_fast_ahb_clk_src",
+			"video_cc_mvs1_clk_src",
+			"disp_cc_mdss_mdp_clk_src",
+			"disp_cc_mdss_dptx0_link_clk_src",
+			"video_cc_mvs0_clk_src";
+		clocks =
+			<&camcc CAM_CC_IFE_0_CLK_SRC>,
+			<&camcc CAM_CC_IFE_1_CLK_SRC>,
+			<&camcc CAM_CC_CSID_CLK_SRC>,
+			<&camcc CAM_CC_IPE_NPS_CLK_SRC>,
+			<&camcc CAM_CC_BPS_CLK_SRC>,
+			<&camcc CAM_CC_IFE_LITE_CLK_SRC>,
+			<&camcc CAM_CC_JPEG_CLK_SRC>,
+			<&camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+			<&camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+			<&camcc CAM_CC_ICP_CLK_SRC>,
+			<&camcc CAM_CC_CPHY_RX_CLK_SRC>,
+			<&camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+			<&camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+			<&camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+			<&camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+			<&camcc CAM_CC_CCI_0_CLK_SRC>,
+			<&camcc CAM_CC_CCI_1_CLK_SRC>,
+			<&camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+			<&camcc CAM_CC_FAST_AHB_CLK_SRC>,
+			<&videocc VIDEO_CC_MVS1_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
+			<&dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+			<&videocc VIDEO_CC_MVS0_CLK_SRC>;
+		clock_rates =
+			/* domain csid lowsvs svs svs_L1 nom turbo */
+			<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 0 727000000 0>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 0 727000000 0>,
+			<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 0 480000000 0>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 0 700000000 0>,
+			<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 0 600000000 0>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 0 480000000 0>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 0 600000000 0>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 0 400000000 0>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 0 480000000 0>,
+			<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 0 600000000 0>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 0 480000000 0>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 0 400000000 0>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 0 37500000 0>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 0 37500000 0>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 0 80000000 0>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 0 400000000 0>,
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 0 1650000000 0>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 0 514000000 0>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 0 810000 0>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 0 1332000000 0>;
+	};
+};
diff --git a/qcom/mmrm/neo-mmrm.dts b/qcom/mmrm/neo-mmrm.dts
new file mode 100644
index 00000000..f2bc0d1e
--- /dev/null
+++ b/qcom/mmrm/neo-mmrm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-neo.h>
+#include <dt-bindings/clock/qcom,videocc-neo.h>
+#include <dt-bindings/clock/qcom,dispcc-neo.h>
+#include "neo-mmrm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. Neo SoC";
+	compatible = "qcom,neo";
+	qcom,msm-id = <554 0x10000>;
+	qcom,board-id = <34 1>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/neo-mmrm.dtsi b/qcom/mmrm/neo-mmrm.dtsi
new file mode 100644
index 00000000..2f641a2a
--- /dev/null
+++ b/qcom/mmrm/neo-mmrm.dtsi
@@ -0,0 +1,42 @@
+&soc {
+	msm_mmrm: qcom,mmrm {
+		compatible = "qcom,msm-mmrm", "qcom,neo-mmrm";
+		status = "okay";
+
+		/* MM Rail info */
+		mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
+		mm-rail-fact-volt = <37487 41157 44827 47711 52429>;
+
+		/* Scaling factors */
+		scaling-fact-dyn = <39951 48654 58347 66677 81757>;
+		scaling-fact-leak = <39951 671797 784172 884468 1082937>;
+
+		/* Client info */
+		mmrm-client-info =
+			<0x1 CAM_CC_IFE_0_CLK_SRC 26581121 174654 1>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 26581121 174654 1>,
+			<0x1 CAM_CC_CSID_CLK_SRC 1858221 0 2>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 51026057 403702 1>,
+			<0x1 CAM_CC_BPS_CLK_SRC 17057081 111412 1>,
+			<0x1 CAM_CC_BPS_CLK_SRC 43645928 0 1>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 1658717 17695 8>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 563610 0 3>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 2930770 275907 1>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 225444 0 8>,
+			<0x1 CAM_CC_ICP_CLK_SRC 270533 0 1>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 191628 0 9>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 5637 0 1>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 564 0 1>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 564 0 1>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 60307 0 1>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 30435 0 1>,
+
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 73400320 835584 1>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 18345493 251659 1>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 912917 5243 1>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 35848192 427295 1>;
+	};
+};
diff --git a/qcom/mmrm/waipio-mmrm-test.dts b/qcom/mmrm/waipio-mmrm-test.dts
new file mode 100644
index 00000000..a52de477
--- /dev/null
+++ b/qcom/mmrm/waipio-mmrm-test.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-waipio.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+#include <dt-bindings/clock/qcom,dispcc-waipio.h>
+#include "waipio-mmrm-test.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. waipio v1 & v2 SoC";
+	compatible = "qcom,waipio";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <552 0x10000>;
+	qcom,board-id = <0 0>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/waipio-mmrm-test.dtsi b/qcom/mmrm/waipio-mmrm-test.dtsi
new file mode 100644
index 00000000..4905c26e
--- /dev/null
+++ b/qcom/mmrm/waipio-mmrm-test.dtsi
@@ -0,0 +1,95 @@
+&soc {
+	msm_mmrm_test: qcom,mmrm-test {
+		compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test";
+		status = "disable";
+
+		/* Clock info */
+		clock-names =
+			"cam_cc_ife_0_clk_src",
+			"cam_cc_ife_1_clk_src",
+			"cam_cc_ife_2_clk_src",
+			"cam_cc_csid_clk_src",
+			"cam_cc_sfe_0_clk_src",
+			"cam_cc_sfe_1_clk_src",
+			"cam_cc_ipe_nps_clk_src",
+			"cam_cc_bps_clk_src",
+			"cam_cc_ife_lite_clk_src",
+			"cam_cc_jpeg_clk_src",
+			"cam_cc_camnoc_axi_clk_src",
+			"cam_cc_ife_lite_csid_clk_src",
+			"cam_cc_icp_clk_src",
+			"cam_cc_cphy_rx_clk_src",
+			"cam_cc_csi0phytimer_clk_src",
+			"cam_cc_csi1phytimer_clk_src",
+			"cam_cc_csi2phytimer_clk_src",
+			"cam_cc_csi3phytimer_clk_src",
+			"cam_cc_csi4phytimer_clk_src",
+			"cam_cc_csi5phytimer_clk_src",
+			"cam_cc_cci_0_clk_src",
+			"cam_cc_cci_1_clk_src",
+			"cam_cc_slow_ahb_clk_src",
+			"cam_cc_fast_ahb_clk_src",
+			"video_cc_mvs1_clk_src",
+			"disp_cc_mdss_mdp_clk_src",
+			"disp_cc_mdss_dptx0_link_clk_src",
+			"video_cc_mvs0_clk_src";
+		clocks =
+			<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_2_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSID_CLK_SRC>,
+			<&clock_camcc CAM_CC_SFE_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_SFE_1_CLK_SRC>,
+			<&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>,
+			<&clock_camcc CAM_CC_BPS_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+			<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
+			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+			<&clock_camcc CAM_CC_ICP_CLK_SRC>,
+			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
+			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+			<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
+			<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+			<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
+		clock_rates =
+			<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
+			<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
+			<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 785000000 785000000>,
+			<0x1 CAM_CC_SFE_1_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
+			<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
+	};
+};
diff --git a/qcom/mmrm/waipio-mmrm.dts b/qcom/mmrm/waipio-mmrm.dts
new file mode 100644
index 00000000..e5dde22e
--- /dev/null
+++ b/qcom/mmrm/waipio-mmrm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-waipio.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+#include <dt-bindings/clock/qcom,dispcc-waipio.h>
+#include "waipio-mmrm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. waipio v1 SoC";
+	compatible = "qcom,waipio";
+	qcom,msm-id = <457 0x10000>, <482 0x10000>, <552 0x10000>;
+	qcom,board-id = <0 0>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/waipio-mmrm.dtsi b/qcom/mmrm/waipio-mmrm.dtsi
new file mode 100644
index 00000000..386bf850
--- /dev/null
+++ b/qcom/mmrm/waipio-mmrm.dtsi
@@ -0,0 +1,46 @@
+&soc {
+	msm_mmrm: qcom,mmrm {
+		compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm";
+		status = "okay";
+
+		/* MM Rail info */
+		mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
+		mm-rail-fact-volt = <36439 41157 44827 49152 54526>;
+
+		/* Scaling factors */
+		scaling-fact-dyn = <35390 45876 54395 66192 82576>;
+		scaling-fact-leak = <451544 548537 633078 746456 920126>;
+
+		/* Client info */
+		mmrm-client-info =
+			<0x1 CAM_CC_IFE_0_CLK_SRC 36280730 260834 1>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 36280730 260834 1>,
+			<0x1 CAM_CC_IFE_2_CLK_SRC 36280730 260834 1>,
+			<0x1 CAM_CC_CSID_CLK_SRC 2160722 0 3>,
+			<0x1 CAM_CC_SFE_0_CLK_SRC 20833895 135660 1>,
+			<0x1 CAM_CC_SFE_1_CLK_SRC 20833895 135660 1>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 67423437 608830 1>,
+			<0x1 CAM_CC_BPS_CLK_SRC 70584894 212992 1>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 1698431 20055 5>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 1011876 0 2>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 3407872 589824 1>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 0 5>,
+			<0x1 CAM_CC_ICP_CLK_SRC 314573 0 1>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 222823 0 9>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 656 0 1>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 656 0 1>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 70124 0 1>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 35390 0 1>,
+
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 81149297 488244 1>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 21954560 184812 1>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1004667 4916 1>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582288 1>;
+	};
+};
diff --git a/qcom/mmrm/waipio-v2-mmrm-test.dts b/qcom/mmrm/waipio-v2-mmrm-test.dts
new file mode 100644
index 00000000..6cbf5938
--- /dev/null
+++ b/qcom/mmrm/waipio-v2-mmrm-test.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-waipio.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+#include <dt-bindings/clock/qcom,dispcc-waipio.h>
+#include "waipio-v2-mmrm-test.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. waipio v1 & v2 SoC";
+	compatible = "qcom,waipio";
+	qcom,msm-id = <457 0x20000>, <482 0x20000>, <552 0x20000>;
+	qcom,board-id = <0 0>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/waipio-v2-mmrm-test.dtsi b/qcom/mmrm/waipio-v2-mmrm-test.dtsi
new file mode 100644
index 00000000..52fc4e12
--- /dev/null
+++ b/qcom/mmrm/waipio-v2-mmrm-test.dtsi
@@ -0,0 +1,95 @@
+&soc {
+	msm_mmrm_test: qcom,mmrm-test {
+		compatible = "qcom,msm-mmrm-test", "qcom,waipio-mmrm-test";
+		status = "disable";
+
+		/* Clock info */
+		clock-names =
+			"cam_cc_ife_0_clk_src",
+			"cam_cc_ife_1_clk_src",
+			"cam_cc_ife_2_clk_src",
+			"cam_cc_csid_clk_src",
+			"cam_cc_sfe_0_clk_src",
+			"cam_cc_sfe_1_clk_src",
+			"cam_cc_ipe_nps_clk_src",
+			"cam_cc_bps_clk_src",
+			"cam_cc_ife_lite_clk_src",
+			"cam_cc_jpeg_clk_src",
+			"cam_cc_camnoc_axi_clk_src",
+			"cam_cc_ife_lite_csid_clk_src",
+			"cam_cc_icp_clk_src",
+			"cam_cc_cphy_rx_clk_src",
+			"cam_cc_csi0phytimer_clk_src",
+			"cam_cc_csi1phytimer_clk_src",
+			"cam_cc_csi2phytimer_clk_src",
+			"cam_cc_csi3phytimer_clk_src",
+			"cam_cc_csi4phytimer_clk_src",
+			"cam_cc_csi5phytimer_clk_src",
+			"cam_cc_cci_0_clk_src",
+			"cam_cc_cci_1_clk_src",
+			"cam_cc_slow_ahb_clk_src",
+			"cam_cc_fast_ahb_clk_src",
+			"video_cc_mvs1_clk_src",
+			"disp_cc_mdss_mdp_clk_src",
+			"disp_cc_mdss_dptx0_link_clk_src",
+			"video_cc_mvs0_clk_src";
+		clocks =
+			<&clock_camcc CAM_CC_IFE_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_1_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_2_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSID_CLK_SRC>,
+			<&clock_camcc CAM_CC_SFE_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_SFE_1_CLK_SRC>,
+			<&clock_camcc CAM_CC_IPE_NPS_CLK_SRC>,
+			<&clock_camcc CAM_CC_BPS_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_LITE_CLK_SRC>,
+			<&clock_camcc CAM_CC_JPEG_CLK_SRC>,
+			<&clock_camcc CAM_CC_CAMNOC_AXI_CLK_SRC>,
+			<&clock_camcc CAM_CC_IFE_LITE_CSID_CLK_SRC>,
+			<&clock_camcc CAM_CC_ICP_CLK_SRC>,
+			<&clock_camcc CAM_CC_CPHY_RX_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI0PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI1PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI2PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI3PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI4PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CSI5PHYTIMER_CLK_SRC>,
+			<&clock_camcc CAM_CC_CCI_0_CLK_SRC>,
+			<&clock_camcc CAM_CC_CCI_1_CLK_SRC>,
+			<&clock_camcc CAM_CC_SLOW_AHB_CLK_SRC>,
+			<&clock_camcc CAM_CC_FAST_AHB_CLK_SRC>,
+			<&clock_videocc VIDEO_CC_MVS1_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_MDP_CLK_SRC>,
+			<&clock_dispcc DISP_CC_MDSS_DPTX0_LINK_CLK_SRC>,
+			<&clock_videocc VIDEO_CC_MVS0_CLK_SRC>;
+		clock_rates =
+			<0x1 CAM_CC_IFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
+			<0x1 CAM_CC_IFE_2_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
+			<0x1 CAM_CC_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_SFE_0_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
+			<0x1 CAM_CC_SFE_1_CLK_SRC 432000000 594000000 675000000 727000000 727000000>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 364000000 500000000 600000000 700000000 700000000>,
+			<0x1 CAM_CC_BPS_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 200000000 400000000 480000000 600000000 600000000>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 300000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_ICP_CLK_SRC 400000000 480000000 600000000 600000000 600000000>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 400000000 480000000 480000000 480000000 480000000>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 400000000 400000000 400000000 400000000 400000000>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 37500000 37500000 37500000 37500000 37500000>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 80000000 80000000 80000000 80000000 80000000>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 100000000 200000000 300000000 400000000 400000000>,
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 1050000000 1350000000 1500000000 1650000000 1650000000>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 200000000 325000000 375000000 500000000 500000000>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 270000 270000 540000 810000 810000>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 720000000 1014000000 1098000000 1332000000 1332000000>;
+	};
+};
diff --git a/qcom/mmrm/waipio-v2-mmrm.dts b/qcom/mmrm/waipio-v2-mmrm.dts
new file mode 100644
index 00000000..b011189d
--- /dev/null
+++ b/qcom/mmrm/waipio-v2-mmrm.dts
@@ -0,0 +1,14 @@
+/dts-v1/;
+/plugin/;
+
+#include <dt-bindings/clock/qcom,camcc-waipio.h>
+#include <dt-bindings/clock/qcom,videocc-waipio.h>
+#include <dt-bindings/clock/qcom,dispcc-waipio.h>
+#include "waipio-v2-mmrm.dtsi"
+
+/ {
+	model = "Qualcomm Technologies, Inc. waipio v2 SoC";
+	compatible = "qcom,waipio";
+	qcom,msm-id = <457 0x20000>, <482 0x20000>, <552 0x20000>;
+	qcom,board-id = <0 0>; /* required by merge_dtbs.py */
+};
diff --git a/qcom/mmrm/waipio-v2-mmrm.dtsi b/qcom/mmrm/waipio-v2-mmrm.dtsi
new file mode 100644
index 00000000..787bab1a
--- /dev/null
+++ b/qcom/mmrm/waipio-v2-mmrm.dtsi
@@ -0,0 +1,45 @@
+&soc {
+	msm_mmrm: qcom,mmrm {
+		compatible = "qcom,msm-mmrm", "qcom,waipio-mmrm";
+		status = "okay";
+
+		/* MM Rail info */
+		mm-rail-corners = "lowsvs", "svs", "svsl1", "nom", "turbo";
+		mm-rail-fact-volt = <36438 41157 44827 49152 54526>;
+
+		/* Scaling factors */
+		scaling-fact-dyn = <35389 45876 54395 66192 82575>;
+		scaling-fact-leak = <451543 548537 633078 746456 920125>;
+
+		/* Client info */
+		mmrm-client-info =
+			<0x1 CAM_CC_IFE_0_CLK_SRC 33751040 279839 1>,
+			<0x1 CAM_CC_IFE_1_CLK_SRC 33751040 279839 1>,
+			<0x1 CAM_CC_IFE_2_CLK_SRC 33751040 279839 1>,
+			<0x1 CAM_CC_CSID_CLK_SRC 2160722 0 3>,
+			<0x1 CAM_CC_SFE_0_CLK_SRC 19333120 132383 1>,
+			<0x1 CAM_CC_SFE_1_CLK_SRC 19333120 132383 1>,
+			<0x1 CAM_CC_IPE_NPS_CLK_SRC 67436544 587203 1>,
+			<0x1 CAM_CC_BPS_CLK_SRC 70584893 334234 1>,
+			<0x1 CAM_CC_IFE_LITE_CLK_SRC 8492155 11796 5>,
+			<0x1 CAM_CC_JPEG_CLK_SRC 1097073 595067 2>,
+			<0x1 CAM_CC_CAMNOC_AXI_CLK_SRC 7602176 3533701 1>,
+			<0x1 CAM_CC_IFE_LITE_CSID_CLK_SRC 262144 0 5>,
+			<0x1 CAM_CC_ICP_CLK_SRC 314573 0 1>,
+			<0x1 CAM_CC_CPHY_RX_CLK_SRC 222822 0 9>,
+			<0x1 CAM_CC_CSI0PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI1PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI2PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI3PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI4PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CSI5PHYTIMER_CLK_SRC 6554 0 1>,
+			<0x1 CAM_CC_CCI_0_CLK_SRC 655 0 1>,
+			<0x1 CAM_CC_CCI_1_CLK_SRC 655 0 1>,
+			<0x1 CAM_CC_SLOW_AHB_CLK_SRC 70124 0 1>,
+			<0x1 CAM_CC_FAST_AHB_CLK_SRC 35389 0 1>,
+			<0x2 VIDEO_CC_MVS1_CLK_SRC 81149297 488243 1>,
+			<0x3 DISP_CC_MDSS_MDP_CLK_SRC 21954560 184812 1>,
+			<0x3 DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 1004667 5243 1>,
+			<0x4 VIDEO_CC_MVS0_CLK_SRC 28970189 582287 1>;
+	};
+};