From 310c5c6abe5d45b8434e32922d1de2aab20cb6fb Mon Sep 17 00:00:00 2001 From: Uttkarsh Aggarwal Date: Thu, 14 Jul 2022 18:40:56 +0530 Subject: [PATCH] ARM: dts: msm: Add ref_clk to PHY node for Anorak This change adds proper ref_clk for PHY to be operational on Anorak. Change-Id: I6a7e72027f9ff49ad2e6091a0146d6a16fa8b6f6 --- qcom/anorak-usb.dtsi | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/qcom/anorak-usb.dtsi b/qcom/anorak-usb.dtsi index 0e8a7f5e..fd19fb72 100644 --- a/qcom/anorak-usb.dtsi +++ b/qcom/anorak-usb.dtsi @@ -79,8 +79,9 @@ vdda33-supply = <&L15B>; qcom,vdd-voltage-level = <0 880000 918750>; - clocks = <&rpmhcc RPMH_CXO_CLK>; - clock-names = "ref_clk_src"; + clocks = <&rpmhcc RPMH_CXO_CLK>, + <&gcc GCC_USB2_0_CLKREF_EN>; + clock-names = "ref_clk_src", "ref_clk"; resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; reset-names = "phy_reset"; @@ -106,10 +107,11 @@ <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK_SRC>, <&usb3_phy_wrapper_gcc_usb30_pipe_clk>, <&rpmhcc RPMH_CXO_CLK>, - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>; + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, + <&gcc GCC_USB3_0_CLKREF_EN>; clock-names = "aux_clk", "pipe_clk", "pipe_clk_mux", "pipe_clk_ext_src", "ref_clk_src", - "com_aux_clk"; + "com_aux_clk", "ref_clk"; resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, <&gcc GCC_USB3_PHY_PRIM_BCR>;