From 43cc4fc0e183200ffaa6b6e506e1b0454a976ca4 Mon Sep 17 00:00:00 2001
From: Kalpak Kawadkar <kkawadka@qti.qualcomm.com>
Date: Fri, 6 May 2022 11:30:48 +0530
Subject: [PATCH 1/2] ARM: dts: msm: Remove few PCIE clocks from protected list
 for NEO

Remove GCC_AGGRE_NOC_PCIE_1_AXI_CLK and GCC_CFG_NOC_PCIE_ANOC_AHB_CLK
clocks from protected clocks on NEO, so that client
can request for the clocks.

Change-Id: Iea2842451b02477854c9119b46b746e60266564a
---
 qcom/neo.dtsi | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/qcom/neo.dtsi b/qcom/neo.dtsi
index 48fced14..bc3b5a4f 100644
--- a/qcom/neo.dtsi
+++ b/qcom/neo.dtsi
@@ -691,8 +691,7 @@
 			<&usb3_phy_wrapper_gcc_usb30_pipe_clk>;
 		clock-names = "bi_tcxo", "sleep_clk",
 			"usb3_phy_wrapper_gcc_usb30_pipe_clk";
-		protected-clocks =  <GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
-				<GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>, <GCC_DDRSS_PCIE_SF_CLK>,
+		protected-clocks =  <GCC_DDRSS_PCIE_SF_CLK>,
 				<GCC_PCIE_0_AUX_CLK>, <GCC_PCIE_0_AUX_CLK_SRC>,
 				<GCC_PCIE_0_CFG_AHB_CLK>, <GCC_PCIE_0_MSTR_AXI_CLK>,
 				<GCC_PCIE_0_PHY_RCHNG_CLK>, <GCC_PCIE_0_PHY_RCHNG_CLK_SRC>,

From 73d6a78f6b6e7ab9a3758cddd8e79fc6bc2223a7 Mon Sep 17 00:00:00 2001
From: Raviteja Laggyshetty <rlaggysh@qti.qualcomm.com>
Date: Fri, 6 May 2022 16:03:21 +0530
Subject: [PATCH 2/2] ARM: dts: msm: Add PCIE_AXI, USB3_PRIM_AXI clock handle
 for NEO

PCIE_AXI, USB3_PRIM_AXI clock node handles are needed for
PCIE master and USB master qos programming respectively.

Change-Id: Idb9e122bd99568a2afc9d5775fb49273659ed023
---
 qcom/neo.dtsi | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/qcom/neo.dtsi b/qcom/neo.dtsi
index bc3b5a4f..c1646d6b 100644
--- a/qcom/neo.dtsi
+++ b/qcom/neo.dtsi
@@ -1258,6 +1258,7 @@
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 		#interconnect-cells = <1>;
+		clocks = <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>;
 	};
 
 	pcie_noc: interconnect@16c0000 {
@@ -1266,6 +1267,8 @@
 		qcom,bcm-voter-names = "hlos";
 		qcom,bcm-voters = <&apps_bcm_voter>;
 		#interconnect-cells = <1>;
+		clocks =  <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>,
+			<&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>;
 	};
 
 	mmss_noc: interconnect@1740000 {