From 357145490744d8462282155fb74c7043066bacb1 Mon Sep 17 00:00:00 2001 From: Prateek Sood Date: Wed, 20 Jan 2021 14:35:34 +0530 Subject: [PATCH] ARM: dts: msm: Add initial device tree for Diwali Add initial device tree to support Diwali on RUMI platform. Change-Id: If2f516b6c07431ebf8d15ae74da08268455380a8 --- bindings/arm/msm/msm.txt | 4 + qcom/Makefile | 8 ++ qcom/diwali-rumi-overlay.dts | 11 ++ qcom/diwali-rumi.dts | 11 ++ qcom/diwali-rumi.dtsi | 14 ++ qcom/diwali.dts | 9 ++ qcom/diwali.dtsi | 266 +++++++++++++++++++++++++++++++++++ 7 files changed, 323 insertions(+) create mode 100644 qcom/diwali-rumi-overlay.dts create mode 100644 qcom/diwali-rumi.dts create mode 100644 qcom/diwali-rumi.dtsi create mode 100644 qcom/diwali.dts create mode 100644 qcom/diwali.dtsi diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 029200e2..5866df9d 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -89,6 +89,9 @@ SoCs: - WAIPIO compatible = "qcom,waipio", "qcom,waipiop" +- DIWALI + compatible = "qcom,diwali" + Generic board variants: - CDP device: @@ -249,3 +252,4 @@ compatible = "qcom,waipio-qrd" compatible = "qcom,waipiop-mtp" compatible = "qcom,waipiop-cdp" compatible = "qcom,waipiop-qrd" +compatible = "qcom,diwali-rumi" diff --git a/qcom/Makefile b/qcom/Makefile index 217cc792..80faffbf 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -101,6 +101,14 @@ dtb-$(CONFIG_ARCH_WAIPIO) += waipio-rumi.dtb \ waipio-qrd-pm8010.dtb endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_DIWALI) += diwali-rumi-overlay.dtbo + +diwali-rumi-overlay.dtbo-base := diwali.dtb +else +dtb-$(CONFIG_ARCH_DIWALI) += diwali-rumi.dtb +endif + ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo dtbo-$(CONFIG_ARCH_HOLI) += holi-rumi-overlay.dtbo \ diff --git a/qcom/diwali-rumi-overlay.dts b/qcom/diwali-rumi-overlay.dts new file mode 100644 index 00000000..c136739d --- /dev/null +++ b/qcom/diwali-rumi-overlay.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/plugin/; + +#include "diwali-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Diwali RUMI"; + compatible = "qcom,diwali-rumi", "qcom,diwali", "qcom,rumi"; + qcom,msm-id = <506 0x10000>; + qcom,board-id = <0x1000F 0>; +}; diff --git a/qcom/diwali-rumi.dts b/qcom/diwali-rumi.dts new file mode 100644 index 00000000..aa1ddcbb --- /dev/null +++ b/qcom/diwali-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00010000; + +#include "diwali.dtsi" +#include "diwali-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Diwali RUMI"; + compatible = "qcom,diwali-rumi", "qcom,diwali", "qcom,rumi"; + qcom,board-id = <0x1000F 0>; +}; diff --git a/qcom/diwali-rumi.dtsi b/qcom/diwali-rumi.dtsi new file mode 100644 index 00000000..9e3c82da --- /dev/null +++ b/qcom/diwali-rumi.dtsi @@ -0,0 +1,14 @@ + +&soc { + timer { + clock-frequency = <500000>; + }; + + timer@17420000 { + clock-frequency = <500000>; + }; + + qcom,wdt@17410000 { + status = "disabled"; + }; +}; diff --git a/qcom/diwali.dts b/qcom/diwali.dts new file mode 100644 index 00000000..af28d46d --- /dev/null +++ b/qcom/diwali.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "diwali.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Diwali SoC"; + compatible = "qcom,diwali"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/diwali.dtsi b/qcom/diwali.dtsi new file mode 100644 index 00000000..4f5b6afe --- /dev/null +++ b/qcom/diwali.dtsi @@ -0,0 +1,266 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Diwali"; + compatible = "qcom,diwali"; + qcom,msm-id = <506 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + + chosen: chosen { }; + + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + reserved_memory: reserved-memory { }; + + aliases { }; + + firmware: firmware { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "psci"; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "psci"; + next-level-cache = <&L2_0>; /* silver L2 sharing */ + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "psci"; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "psci"; + next-level-cache = <&L2_2>; /* silver L2 sharing */ + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "psci"; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "psci"; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU6: cpu@600 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x600>; + enable-method = "psci"; + next-level-cache = <&L2_6>; + L2_6: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU7: cpu@700 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x700>; + enable-method = "psci"; + next-level-cache = <&L2_7>; + L2_7: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + + core2 { + cpu = <&CPU2>; + }; + + core3 { + cpu = <&CPU3>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU4>; + }; + + core1 { + cpu = <&CPU5>; + }; + + core2 { + cpu = <&CPU6>; + }; + }; + + cluster2 { + core0 { + cpu = <&CPU7>; + }; + }; + }; + }; + + soc: soc { }; +}; + +&firmware { + qcom_scm { + compatible = "qcom,scm"; + }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17100000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x40000>; + reg = <0x17100000 0x10000>, /* GICD */ + <0x17180000 0x200000>; /* GICR * 8 */ + interrupts = ; + }; + + wdog: qcom,wdt@17410000 { + compatible = "qcom,msm-watchdog"; + reg = <0x17410000 0x1000>; + reg-names = "wdt-base"; + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; +};