From 38171c3f38768424255296bcc69c52ea4605ce71 Mon Sep 17 00:00:00 2001
From: Faiz Nabi Kuchay <fkuchay@qti.qualcomm.com>
Date: Wed, 19 Oct 2022 14:36:20 +0530
Subject: [PATCH] ARM: dts: msm: Add WSA and WCD reset pin support on ravelin

Add WSA and WCD reset pin support on ravelin.

Change-Id: I635aca8314da0ba7b54505a477af8010f57a1770
---
 qcom/ravelin-pinctrl.dtsi | 89 +++++++++++++++++++++++++++++++++++++++
 qcom/ravelin.dtsi         |  2 +-
 2 files changed, 90 insertions(+), 1 deletion(-)

diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi
index d28db4ab..272534b0 100644
--- a/qcom/ravelin-pinctrl.dtsi
+++ b/qcom/ravelin-pinctrl.dtsi
@@ -50,6 +50,95 @@
 			};
 		};
 
+		/* WSA speaker reset pins */
+		spkr_1_sd_n {
+			spkr_1_sd_n_sleep: spkr_1_sd_n_sleep {
+				mux {
+					pins = "gpio99";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio99";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;
+					input-enable;
+				};
+			};
+
+			spkr_1_sd_n_active: spkr_1_sd_n_active {
+				mux {
+					pins = "gpio99";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio99";
+					drive-strength = <16>;   /* 16 mA */
+					bias-disable;
+					output-high;
+				};
+			};
+		};
+
+		spkr_2_sd_n {
+			spkr_2_sd_n_sleep: spkr_2_sd_n_sleep {
+				mux {
+					pins = "gpio100";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio100";
+					drive-strength = <2>;   /* 2 mA */
+					bias-pull-down;
+					input-enable;
+				};
+			};
+
+			spkr_2_sd_n_active: spkr_2_sd_n_active {
+				mux {
+					pins = "gpio100";
+					function = "gpio";
+				};
+
+				config {
+					pins = "gpio100";
+					drive-strength = <16>;   /* 16 mA */
+					bias-disable;
+					output-high;
+				};
+			};
+		};
+
+		/* WCD reset pin */
+		wcd_reset_active: wcd_reset_active {
+			mux {
+				pins = "gpio96";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio96";
+				drive-strength = <16>;
+				output-high;
+			};
+		};
+
+		wcd_reset_sleep: wcd_reset_sleep {
+			mux {
+				pins = "gpio96";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio96";
+				drive-strength = <16>;
+				bias-disable;
+				output-low;
+			};
+		};
+
 		sdc1_on: sdc1_on {
 			clk {
 				pins = "sdc1_clk";
diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi
index 50b47ee2..38aaf17f 100644
--- a/qcom/ravelin.dtsi
+++ b/qcom/ravelin.dtsi
@@ -37,7 +37,7 @@
 		mboxes = <&qmp_aop 0>;
 	};
 
-	aliases {
+	aliases: aliases {
 		serial0 = &qupv3_se2_2uart;
 		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
 		mmc0 = &sdhc_1; /*SDC1 eMMC slot*/