diff --git a/qcom/cape-usb.dtsi b/qcom/cape-usb.dtsi
index b8d2c8a2..6ec41e10 100644
--- a/qcom/cape-usb.dtsi
+++ b/qcom/cape-usb.dtsi
@@ -144,172 +144,171 @@
 			 USB3_DP_PCS_AON_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1                  0x55 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1                   0x0E 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1                          0x02 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1                        0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1                        0x36 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1                      0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1                        0x2E 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1                        0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1                        0x04 0
-			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1                    0x01 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1                  0x55 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1                  0xD5 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1                  0x05 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL_1                            0x01 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1                        0x25 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1                        0x02 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1             0xB7 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1             0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0             0xB7 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0             0x1E 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0                   0x55 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0                   0x0E 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0                          0x02 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0                        0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0                        0x36 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0                        0x12 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0                        0x34 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0                        0x04 0
-			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0                    0x01 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0                  0x55 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0                  0xD5 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0                  0x05 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0                        0x25 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0                        0x02 0
-			USB3_DP_QSERDES_COM_BG_TIMER                               0x0E 0
-			USB3_DP_QSERDES_COM_SSC_EN_CENTER                          0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1                               0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2                               0x01 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE                      0x0C 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL                          0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_CFG                           0x14 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP                           0x04 0
-			USB3_DP_QSERDES_COM_CORE_CLK_EN                            0x20 0
-			USB3_DP_QSERDES_COM_CMN_CONFIG_1                           0x04 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1                   0xB6 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2                   0x4B 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3                   0x37 0
-			USB3_DP_QSERDES_COM_ADDITIONAL_MISC                        0x0C 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX                       0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX                       0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX                0x1F 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX                0x09 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1                            0xF5 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3                            0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4                            0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5                            0x5F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2                       0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL                            0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN                           0x0A 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN                           0x06 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN                  0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE          0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW                0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH               0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS                       0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1                       0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2                       0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1                         0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2                         0x08 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE                 0xA0 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1                         0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2                         0x0F 0
-			USB3_DP_QSERDES_RXA_GM_CAL                                 0x13 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2                  0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3                  0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4                  0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW                    0x07 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH                   0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1            0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL                           0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL                  0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW                         0x3F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH                        0xFF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2                       0xFF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3                       0xDF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4                       0xFE 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW                         0xDC 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH                        0x5C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2                       0x9C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3                       0x1D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4                       0x09 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER                           0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET               0x38 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1                              0x0C 0
-			USB3_DP_QSERDES_RXA_VTH_CODE                               0x10 0
-			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1                       0x14 0
-			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM                        0x08 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX                       0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX                       0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX                0x1F 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX                0x09 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1                            0xF5 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3                            0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4                            0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5                            0x5F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2                       0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL                            0x05 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN                           0x0A 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN                           0x06 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN                  0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE          0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW                0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH               0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS                       0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1                       0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2                       0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1                         0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2                         0x08 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE                 0xA0 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1                         0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2                         0x0F 0
-			USB3_DP_QSERDES_RXB_GM_CAL                                 0x13 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2                  0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3                  0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4                  0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW                    0x07 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH                   0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1            0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL                           0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL                  0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW                         0x3F 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH                        0xFF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2                       0xFF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3                       0xDF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4                       0xFE 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW                         0xDC 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH                        0x5C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2                       0x9C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3                       0x1D 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4                       0x09 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER                           0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET               0x38 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1                              0x0C 0
-			USB3_DP_QSERDES_RXB_VTH_CODE                               0x10 0
-			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1                       0x14 0
-			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM                        0x08 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1                            0xC4 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2                            0x89 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3                            0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6                            0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1                             0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL                                  0x99 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L                           0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H                           0x03 0
-			USB3_DP_PCS_CDR_RESET_TIME                                 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1                           0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2                           0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG                               0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1                                     0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5                                     0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL                   0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2                  0x07 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L                        0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H                        0x00 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1                  0x55
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1                   0x0E
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1                          0x02
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1                        0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1                        0x36
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1                      0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1                        0x2E
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1                        0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1                        0x04
+			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1                    0x01
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1                  0x55
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1                  0xD5
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1                  0x05
+			USB3_DP_QSERDES_COM_HSCLK_SEL_1                            0x01
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1                        0x25
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1                        0x02
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1             0xB7
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1             0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0             0xB7
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0             0x1E
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0                   0x55
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0                   0x0E
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0                          0x02
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0                        0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0                        0x36
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0                        0x12
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0                        0x34
+			USB3_DP_QSERDES_COM_DEC_START_MODE0                        0x04
+			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0                    0x01
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0                  0x55
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0                  0xD5
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0                  0x05
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0                        0x25
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0                        0x02
+			USB3_DP_QSERDES_COM_BG_TIMER                               0x0E
+			USB3_DP_QSERDES_COM_SSC_EN_CENTER                          0x01
+			USB3_DP_QSERDES_COM_SSC_PER1                               0x31
+			USB3_DP_QSERDES_COM_SSC_PER2                               0x01
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE                      0x0C
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL                          0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_CFG                           0x14
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP                           0x04
+			USB3_DP_QSERDES_COM_CORE_CLK_EN                            0x20
+			USB3_DP_QSERDES_COM_CMN_CONFIG_1                           0x04
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1                   0xB6
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2                   0x4B
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3                   0x37
+			USB3_DP_QSERDES_COM_ADDITIONAL_MISC                        0x0C
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX                       0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX                       0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX                0x1F
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX                0x09
+			USB3_DP_QSERDES_TXA_LANE_MODE_1                            0xF5
+			USB3_DP_QSERDES_TXA_LANE_MODE_3                            0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4                            0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5                            0x5F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2                       0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL                            0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN                           0x0A
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN                           0x06
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN                  0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE          0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW                0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH               0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS                       0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1                       0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2                       0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1                         0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2                         0x08
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE                 0xA0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1                         0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2                         0x0F
+			USB3_DP_QSERDES_RXA_GM_CAL                                 0x13
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2                  0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3                  0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4                  0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW                    0x07
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH                   0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1            0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL                           0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL                  0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW                         0x3F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH                        0xFF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2                       0xFF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3                       0xDF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4                       0xFE
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW                         0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH                        0x5C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2                       0x9C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3                       0x1D
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4                       0x09
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER                           0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET               0x38
+			USB3_DP_QSERDES_RXA_DCC_CTRL1                              0x0C
+			USB3_DP_QSERDES_RXA_VTH_CODE                               0x10
+			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1                       0x14
+			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM                        0x08
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX                       0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX                       0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX                0x1F
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX                0x09
+			USB3_DP_QSERDES_TXB_LANE_MODE_1                            0xF5
+			USB3_DP_QSERDES_TXB_LANE_MODE_3                            0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4                            0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5                            0x5F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2                       0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL                            0x05
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN                           0x0A
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN                           0x06
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN                  0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE          0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW                0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH               0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS                       0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1                       0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2                       0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1                         0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2                         0x08
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE                 0xA0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1                         0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2                         0x0F
+			USB3_DP_QSERDES_RXB_GM_CAL                                 0x13
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2                  0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3                  0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4                  0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW                    0x07
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH                   0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1            0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL                           0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL                  0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW                         0x3F
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH                        0xFF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2                       0xFF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3                       0xDF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4                       0xFE
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW                         0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH                        0x5C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2                       0x9C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3                       0x1D
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4                       0x09
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER                           0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET               0x38
+			USB3_DP_QSERDES_RXB_DCC_CTRL1                              0x0C
+			USB3_DP_QSERDES_RXB_VTH_CODE                               0x10
+			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1                       0x14
+			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM                        0x08
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1                            0xC4
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2                            0x89
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3                            0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6                            0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1                             0x21
+			USB3_DP_PCS_RX_SIGDET_LVL                                  0x99
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L                           0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H                           0x03
+			USB3_DP_PCS_CDR_RESET_TIME                                 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1                           0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2                           0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG                               0x0C
+			USB3_DP_PCS_EQ_CONFIG1                                     0x4B
+			USB3_DP_PCS_EQ_CONFIG5                                     0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL                   0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2                  0x07
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L                        0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H                        0x00>;
 	};
 
 	usb_nop_phy: usb_nop_phy {
diff --git a/qcom/diwali-usb.dtsi b/qcom/diwali-usb.dtsi
index 51cb8c49..aa4d7630 100644
--- a/qcom/diwali-usb.dtsi
+++ b/qcom/diwali-usb.dtsi
@@ -169,160 +169,159 @@
 			 USB3_DP_PCS_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
-			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
-			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
-			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5 0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_GM_CAL 0x00
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_GM_CAL 0x00
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0xAA
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
 	};
 
 	usb_audio_qmi_dev {
diff --git a/qcom/neo-usb.dtsi b/qcom/neo-usb.dtsi
index 53375bd4..90a6ba33 100644
--- a/qcom/neo-usb.dtsi
+++ b/qcom/neo-usb.dtsi
@@ -138,171 +138,170 @@
 			 USB3_DP_PCS_AON_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x55 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x0E 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1			0x02 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1			0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1			0x36 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1			0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1			0x2E 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1			0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1			0x04 0
-			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1			0x01 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1		0x55 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1		0xD5 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1		0x05 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL_1				0x01 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1			0x25 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1			0x02 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1		0xB7 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1		0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0		0xB7 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0		0x1E 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x55 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x0E 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0			0x02 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0			0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0			0x36 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0			0x12 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0			0x34 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0			0x04 0
-			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0			0x01 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0		0x55 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0		0xD5 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0		0x05 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0			0x25 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0			0x02 0
-			USB3_DP_QSERDES_COM_BG_TIMER				0x0E 0
-			USB3_DP_QSERDES_COM_SSC_EN_CENTER			0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1				0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2				0x01 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE			0x0C 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL			0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_CFG			0x14 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP			0x04 0
-			USB3_DP_QSERDES_COM_CORE_CLK_EN				0x20 0
-			USB3_DP_QSERDES_COM_CMN_CONFIG_1			0x04 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1		0xB6 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2		0x4B 0
-			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3		0x37 0
-			USB3_DP_QSERDES_COM_ADDITIONAL_MISC			0x0C 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX			0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX			0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX		0x1F 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX		0x09 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1				0xF5 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3				0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4				0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5				0x5F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2			0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL				0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN			0x0A 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN			0x06 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN		0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE	0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW		0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH		0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS			0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1			0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2			0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1			0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2			0x0A 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE		0xA0 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1			0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2			0x0F 0
-			USB3_DP_QSERDES_RXA_GM_CAL				0x13 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2		0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3		0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4		0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW			0x07 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH		0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL			0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL		0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW			0x3F 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH			0xBF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2			0xFF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3			0xDF 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4			0xED 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW			0xDC 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH			0x5C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2			0x9C 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3			0x1D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4			0x09 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER			0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET		0x38 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1				0x0C 0
-			USB3_DP_QSERDES_RXA_VTH_CODE				0x10 0
-			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1			0x14 0
-			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM			0x08 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX			0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX			0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX		0x1F 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX		0x09 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1				0xF5 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3				0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4				0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5				0x5F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2			0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL				0x05 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN			0x0A 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN			0x06 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN		0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE	0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW		0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH		0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS			0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1			0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2			0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1			0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2			0x0A 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE		0xA0 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1			0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2			0x0F 0
-			USB3_DP_QSERDES_RXB_GM_CAL				0x13 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2		0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3		0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4		0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW			0x07 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH		0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL			0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL		0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW			0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH			0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2			0xBF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3			0xDF 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4			0xFD 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW			0xDC 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH			0x5C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2			0x9C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3			0x1D 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4			0x09 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER			0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET		0x38 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1				0x0C 0
-			USB3_DP_QSERDES_RXB_VTH_CODE				0x10 0
-			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1			0x14 0
-			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM			0x08 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1				0xC4 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2				0x89 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3				0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6				0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1				0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL				0xAA 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L			0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H			0x03 0
-			USB3_DP_PCS_CDR_RESET_TIME				0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1			0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2			0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG				0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1					0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5					0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL		0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2		0x07 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L			0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H			0x00 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1		0x55
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1		0x0E
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1			0x02
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1			0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1			0x36
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1			0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1			0x2E
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1			0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1			0x04
+			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE1			0x01
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1		0x55
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1		0xD5
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1		0x05
+			USB3_DP_QSERDES_COM_HSCLK_SEL_1				0x01
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1			0x25
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1			0x02
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1		0xB7
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1		0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0		0xB7
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0		0x1E
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0		0x55
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0		0x0E
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0			0x02
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0			0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0			0x36
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0			0x12
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0			0x34
+			USB3_DP_QSERDES_COM_DEC_START_MODE0			0x04
+			USB3_DP_QSERDES_COM_DEC_START_MSB_MODE0			0x01
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0		0x55
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0		0xD5
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0		0x05
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0			0x25
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE0			0x02
+			USB3_DP_QSERDES_COM_BG_TIMER				0x0E
+			USB3_DP_QSERDES_COM_SSC_EN_CENTER			0x01
+			USB3_DP_QSERDES_COM_SSC_PER1				0x31
+			USB3_DP_QSERDES_COM_SSC_PER2				0x01
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE			0x0C
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL			0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_CFG			0x14
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP			0x04
+			USB3_DP_QSERDES_COM_CORE_CLK_EN				0x20
+			USB3_DP_QSERDES_COM_CMN_CONFIG_1			0x04
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_1		0xB6
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_2		0x4B
+			USB3_DP_QSERDES_COM_AUTO_GAIN_ADJ_CTRL_3		0x37
+			USB3_DP_QSERDES_COM_ADDITIONAL_MISC			0x0C
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX			0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX			0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX		0x1F
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX		0x09
+			USB3_DP_QSERDES_TXA_LANE_MODE_1				0xF5
+			USB3_DP_QSERDES_TXA_LANE_MODE_3				0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4				0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5				0x5F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2			0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL				0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN			0x0A
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN			0x06
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN		0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE	0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW		0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH		0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS			0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1			0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2			0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1			0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2			0x0A
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE		0xA0
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1			0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2			0x0F
+			USB3_DP_QSERDES_RXA_GM_CAL				0x13
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2		0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3		0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4		0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW			0x07
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH		0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL			0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL		0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW			0x3F
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH			0xBF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2			0xFF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3			0xDF
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4			0xED
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW			0xDC
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH			0x5C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2			0x9C
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3			0x1D
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4			0x09
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER			0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET		0x38
+			USB3_DP_QSERDES_RXA_DCC_CTRL1				0x0C
+			USB3_DP_QSERDES_RXA_VTH_CODE				0x10
+			USB3_DP_QSERDES_RXA_SIGDET_CAL_CTRL1			0x14
+			USB3_DP_QSERDES_RXA_SIGDET_CAL_TRIM			0x08
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX			0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX			0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX		0x1F
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX		0x09
+			USB3_DP_QSERDES_TXB_LANE_MODE_1				0xF5
+			USB3_DP_QSERDES_TXB_LANE_MODE_3				0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4				0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5				0x5F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2			0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL				0x05
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN			0x0A
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN			0x06
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN		0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE	0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW		0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH		0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS			0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1			0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2			0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1			0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2			0x0A
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE		0xA0
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1			0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2			0x0F
+			USB3_DP_QSERDES_RXB_GM_CAL				0x13
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2		0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3		0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4		0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW			0x07
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH		0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1		0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL			0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL		0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW			0xBF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH			0xBF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2			0xBF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3			0xDF
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4			0xFD
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW			0xDC
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH			0x5C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2			0x9C
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3			0x1D
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4			0x09
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER			0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET		0x38
+			USB3_DP_QSERDES_RXB_DCC_CTRL1				0x0C
+			USB3_DP_QSERDES_RXB_VTH_CODE				0x10
+			USB3_DP_QSERDES_RXB_SIGDET_CAL_CTRL1			0x14
+			USB3_DP_QSERDES_RXB_SIGDET_CAL_TRIM			0x08
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1				0xC4
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2				0x89
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3				0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6				0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1				0x21
+			USB3_DP_PCS_RX_SIGDET_LVL				0xAA
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L			0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H			0x03
+			USB3_DP_PCS_CDR_RESET_TIME				0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1			0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2			0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG				0x0C
+			USB3_DP_PCS_EQ_CONFIG1					0x4B
+			USB3_DP_PCS_EQ_CONFIG5					0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL		0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2		0x07
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L			0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H			0x00>;
 	};
 };
diff --git a/qcom/parrot-usb.dtsi b/qcom/parrot-usb.dtsi
index 97417409..498b29ee 100644
--- a/qcom/parrot-usb.dtsi
+++ b/qcom/parrot-usb.dtsi
@@ -139,160 +139,159 @@
 			 USB3_DP_PCS_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
-			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
-			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
-			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5 0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_GM_CAL 0x00
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_GM_CAL 0x00
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0xAA
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
 	};
 
 	usb_audio_qmi_dev {
diff --git a/qcom/waipio-usb.dtsi b/qcom/waipio-usb.dtsi
index 37c7e149..1289500a 100644
--- a/qcom/waipio-usb.dtsi
+++ b/qcom/waipio-usb.dtsi
@@ -171,160 +171,159 @@
 			 USB3_DP_PCS_CLAMP_ENABLE>;
 
 		qcom,qmp-phy-init-seq =
-			/* <reg_offset, value, delay> */
-			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01 0
-			USB3_DP_QSERDES_COM_SSC_PER1 0x31 0
-			USB3_DP_QSERDES_COM_SSC_PER2 0x01 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE 0
-			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07 0
-			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A 0
-			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06 0
-			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16 0
-			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36 0
-			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36 0
-			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A 0
-			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34 0
-			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82 0
-			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA 0
-			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24 0
-			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02 0
-			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01 0
-			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E 0
-			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D 0
-			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXA_GM_CAL 0x00 0
-			USB3_DP_QSERDES_RXA_VTH_CODE 0x10 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16 0
-			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F 0
-			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F 0
-			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12 0
-			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21 0
-			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F 0
-			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF 0
-			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F 0
-			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00 0
-			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54 0
-			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A 0
-			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0 0
-			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00 0
-			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47 0
-			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04 0
-			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C 0
-			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13 0
-			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9 0
-			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04 0
-			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38 0
-			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0 0
-			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C 0
-			USB3_DP_QSERDES_RXB_GM_CAL 0x00 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40 0
-			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7 0
-			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03 0
-			USB3_DP_QSERDES_RXB_VTH_CODE 0x10 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20 0
-			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13 0
-			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21 0
-			USB3_DP_PCS_RX_SIGDET_LVL 0xAA 0
-			USB3_DP_PCS_CDR_RESET_TIME 0x0A 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88 0
-			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13 0
-			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C 0
-			USB3_DP_PCS_EQ_CONFIG1 0x4B 0
-			USB3_DP_PCS_EQ_CONFIG5 0x10 0
-			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8 0
-			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07 0
-			0xffffffff 0xffffffff 0x00>;
+			/* <reg_offset, value> */
+			<USB3_DP_QSERDES_COM_SSC_EN_CENTER 0x01
+			USB3_DP_QSERDES_COM_SSC_PER1 0x31
+			USB3_DP_QSERDES_COM_SSC_PER2 0x01
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE0 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE0 0x07
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE1_MODE1 0xDE
+			USB3_DP_QSERDES_COM_SSC_STEP_SIZE2_MODE1 0x07
+			USB3_DP_QSERDES_COM_SYSCLK_BUF_ENABLE 0x0A
+			USB3_DP_QSERDES_COM_CMN_IPTRIM 0x20
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE0 0x06
+			USB3_DP_QSERDES_COM_CP_CTRL_MODE1 0x06
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE0 0x16
+			USB3_DP_QSERDES_COM_PLL_RCTRL_MODE1 0x16
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE0 0x36
+			USB3_DP_QSERDES_COM_PLL_CCTRL_MODE1 0x36
+			USB3_DP_QSERDES_COM_SYSCLK_EN_SEL 0x1A
+			USB3_DP_QSERDES_COM_LOCK_CMP_EN 0x04
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE0 0x14
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE0 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP1_MODE1 0x34
+			USB3_DP_QSERDES_COM_LOCK_CMP2_MODE1 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE0 0x82
+			USB3_DP_QSERDES_COM_DEC_START_MODE1 0x82
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE0 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE0 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE0 0x02
+			USB3_DP_QSERDES_COM_DIV_FRAC_START1_MODE1 0xAB
+			USB3_DP_QSERDES_COM_DIV_FRAC_START2_MODE1 0xEA
+			USB3_DP_QSERDES_COM_DIV_FRAC_START3_MODE1 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE_MAP 0x02
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE0 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE1_MODE1 0x24
+			USB3_DP_QSERDES_COM_VCO_TUNE2_MODE1 0x02
+			USB3_DP_QSERDES_COM_HSCLK_SEL 0x01
+			USB3_DP_QSERDES_COM_CORECLK_DIV_MODE1 0x08
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0xCA
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1E
+			USB3_DP_QSERDES_COM_BIN_VCOCAL_HSCLK_SEL 0x11
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXA_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXA_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXA_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXA_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXA_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXA_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXA_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXA_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXA_UCDR_SO_GAIN 0x04
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXA_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXA_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXA_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXA_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXA_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXA_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXA_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXA_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXA_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXA_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXA_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH3 0x3D
+			USB3_DP_QSERDES_RXA_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXA_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXA_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXA_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXA_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXA_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXA_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXA_GM_CAL 0x00
+			USB3_DP_QSERDES_RXA_VTH_CODE 0x10
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_TX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_RX 0x00
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_TX 0x16
+			USB3_DP_QSERDES_TXB_RES_CODE_LANE_OFFSET_RX 0x0E
+			USB3_DP_QSERDES_TXB_LANE_MODE_1 0x35
+			USB3_DP_QSERDES_TXB_LANE_MODE_3 0x3F
+			USB3_DP_QSERDES_TXB_LANE_MODE_4 0x7F
+			USB3_DP_QSERDES_TXB_LANE_MODE_5 0x3F
+			USB3_DP_QSERDES_TXB_RCV_DETECT_LVL_2 0x12
+			USB3_DP_QSERDES_TXB_PI_QEC_CTRL 0x21
+			USB3_DP_QSERDES_RXB_UCDR_FO_GAIN 0x09
+			USB3_DP_QSERDES_RXB_UCDR_SO_GAIN 0x04
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_FO_GAIN 0x2F
+			USB3_DP_QSERDES_RXB_UCDR_SO_SATURATION_AND_ENABLE 0x7F
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_LOW 0xFF
+			USB3_DP_QSERDES_RXB_UCDR_FASTLOCK_COUNT_HIGH 0x0F
+			USB3_DP_QSERDES_RXB_UCDR_PI_CONTROLS 0x99
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH1 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_THRESH2 0x08
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN1 0x00
+			USB3_DP_QSERDES_RXB_UCDR_SB2_GAIN2 0x04
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL1 0x54
+			USB3_DP_QSERDES_RXB_VGA_CAL_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL2 0x0F
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL3 0x4A
+			USB3_DP_QSERDES_RXB_RX_EQU_ADAPTOR_CNTRL4 0x0A
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_LOW 0xC0
+			USB3_DP_QSERDES_RXB_RX_IDAC_TSETTLE_HIGH 0x00
+			USB3_DP_QSERDES_RXB_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x47
+			USB3_DP_QSERDES_RXB_SIGDET_CNTRL 0x04
+			USB3_DP_QSERDES_RXB_SIGDET_DEGLITCH_CNTRL 0x0E
+			USB3_DP_QSERDES_RXB_RX_MODE_00_LOW 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH 0x7B
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH2 0xBB
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH3 0x3C
+			USB3_DP_QSERDES_RXB_RX_MODE_00_HIGH4 0xDB
+			USB3_DP_QSERDES_RXB_RX_MODE_01_LOW 0x64
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH 0x24
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH2 0xD2
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH3 0x13
+			USB3_DP_QSERDES_RXB_RX_MODE_01_HIGH4 0xA9
+			USB3_DP_QSERDES_RXB_DFE_EN_TIMER 0x04
+			USB3_DP_QSERDES_RXB_DFE_CTLE_POST_CAL_OFFSET 0x38
+			USB3_DP_QSERDES_RXB_AUX_DATA_TCOARSE_TFINE 0xA0
+			USB3_DP_QSERDES_RXB_DCC_CTRL1 0x0C
+			USB3_DP_QSERDES_RXB_GM_CAL 0x00
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x40
+			USB3_DP_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x00
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_L 0xE7
+			USB3_DP_PCS_RCVR_DTCT_DLY_P1U2_H 0x03
+			USB3_DP_QSERDES_RXB_VTH_CODE 0x10
+			USB3_DP_PCS_LOCK_DETECT_CONFIG1 0xC4
+			USB3_DP_PCS_LOCK_DETECT_CONFIG2 0x89
+			USB3_DP_PCS_LOCK_DETECT_CONFIG3 0x20
+			USB3_DP_PCS_LOCK_DETECT_CONFIG6 0x13
+			USB3_DP_PCS_REFGEN_REQ_CONFIG1 0x21
+			USB3_DP_PCS_RX_SIGDET_LVL 0xAA
+			USB3_DP_PCS_CDR_RESET_TIME 0x0A
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG1 0x88
+			USB3_DP_PCS_ALIGN_DETECT_CONFIG2 0x13
+			USB3_DP_PCS_PCS_TX_RX_CONFIG 0x0C
+			USB3_DP_PCS_EQ_CONFIG1 0x4B
+			USB3_DP_PCS_EQ_CONFIG5 0x10
+			USB3_DP_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0xF8
+			USB3_DP_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x07>;
 	};
 
 	usb_audio_qmi_dev {