From a004c47d97cdf9942b267b306f157c8313483d69 Mon Sep 17 00:00:00 2001
From: Amrit Anand <amrianan@qti.qualcomm.com>
Date: Wed, 17 Nov 2021 10:19:55 +0530
Subject: [PATCH] ARM: dts: msm: Add LLCC node for Neo

Add LLCC node for Neo to enable Last Level Cache Controller.

Change-Id: Ic87480f9719c704ccd478f0251dee097288b6abf
---
 qcom/neo.dtsi | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/qcom/neo.dtsi b/qcom/neo.dtsi
index a7b2ddf6..065b8bd2 100644
--- a/qcom/neo.dtsi
+++ b/qcom/neo.dtsi
@@ -395,6 +395,13 @@
 			status = "disabled";
 		};
 	};
+	cache-controller@19200000 {
+		compatible = "qcom,neo-llcc", "qcom,llcc-v31";
+		reg = <0x19200000 0x180000> , <0x19A00000 0x80000>;
+		reg-names = "llcc_base", "llcc_broadcast_base";
+		interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>;
+		cap-based-alloc-and-pwr-collapse;
+	};
 
 	clocks {
 		xo_board: xo_board {