From 3aaea510b90057e8fe32fd29ec26230f5088511c Mon Sep 17 00:00:00 2001 From: Jack Pham Date: Fri, 25 Oct 2019 13:12:12 -0700 Subject: [PATCH] ARM: dts: msm: Update USB device nodes on Lahaina Switch USB devices' compatible strings to "qcom,dwc-usb3-msm" which corresponds to dwc3-msm driver which supports more features than the upstream dwc3-qcom driver. Base addresses are updated accordingly and additional properties are added. Change-Id: Ia5188ba9bd7b6b6835e2ac0001d2de0fbda35ed3 --- qcom/lahaina-usb.dtsi | 67 ++++++++++++++++++++++++++++++++++--------- 1 file changed, 54 insertions(+), 13 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index b69c8fb3..8bbe807d 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -1,7 +1,7 @@ &soc { - usb0: ssusb@a6f8800 { - compatible = "qcom,dwc3"; - reg = <0xa6f8800 0x400>; + usb0: ssusb@a600000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa600000 0x100000>; reg-names = "core_base"; iommus = <&apps_smmu 0x0 0x0>; @@ -12,6 +12,14 @@ ranges; dma-ranges; + interrupts-extended = <&pdc 14 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 15 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + USB3_GDSC-supply = <&gcc_usb30_prim_gdsc>; clocks = <&clock_gcc GCC_USB30_PRIM_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, @@ -24,6 +32,18 @@ resets = <&clock_gcc GCC_USB30_PRIM_BCR>; reset-names = "core_reset"; + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + dwc3@a600000 { compatible = "snps,dwc3"; reg = <0xa600000 0xcd00>; @@ -32,8 +52,8 @@ snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; usb-core-id = <0>; @@ -43,9 +63,9 @@ }; }; - usb1: ssusb@a8f8800 { - compatible = "qcom,dwc3"; - reg = <0xa8f8800 0x400>; + usb1: ssusb@a800000 { + compatible = "qcom,dwc-usb3-msm"; + reg = <0xa800000 0x100000>; reg-names = "core_base"; iommus = <&apps_smmu 0x20 0x0>; @@ -56,18 +76,39 @@ ranges; dma-ranges; + interrupts-extended = <&pdc 12 IRQ_TYPE_EDGE_BOTH>, + <&intc GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 16 IRQ_TYPE_LEVEL_HIGH>, + <&pdc 13 IRQ_TYPE_EDGE_BOTH>; + interrupt-names = "dp_hs_phy_irq", "pwr_event_irq", + "ss_phy_irq", "dm_hs_phy_irq"; + qcom,use-pdc-interrupts; + USB3_GDSC-supply = <&gcc_usb30_sec_gdsc>; clocks = <&clock_gcc GCC_USB30_SEC_MASTER_CLK>, <&clock_gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, <&clock_gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, <&clock_gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, - <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>; + <&clock_gcc GCC_USB30_SEC_SLEEP_CLK>, + <&clock_gcc GCC_USB3_SEC_CLKREF_EN>; clock-names = "core_clk", "iface_clk", "bus_aggr_clk", - "utmi_clk", "sleep_clk"; + "utmi_clk", "sleep_clk", "xo"; resets = <&clock_gcc GCC_USB30_SEC_BCR>; reset-names = "core_reset"; + qcom,core-clk-rate = <200000000>; + qcom,core-clk-rate-hs = <66666667>; + qcom,num-gsi-evt-buffs = <0x3>; + qcom,gsi-reg-offset = + <0x0fc /* GSI_GENERAL_CFG */ + 0x110 /* GSI_DBL_ADDR_L */ + 0x120 /* GSI_DBL_ADDR_H */ + 0x130 /* GSI_RING_BASE_ADDR_L */ + 0x144 /* GSI_RING_BASE_ADDR_H */ + 0x1a4>; /* GSI_IF_STS */ + qcom,dwc-usb3-msm-tx-fifo-size = <27696>; + dwc3@a800000 { compatible = "snps,dwc3"; reg = <0xa800000 0xcd00>; @@ -76,11 +117,11 @@ snps,disable-clk-gating; snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; - snps,ssp-u3-u0-quirk; - snps,usb3-u1u2-disable; + snps,dis-u1-entry-quirk; + snps,dis-u2-entry-quirk; snps,dis_u2_susphy_quirk; snps,dis_enblslpm_quirk; - usb-core-id = <0>; + usb-core-id = <1>; tx-fifo-resize; maximum-speed = "super-speed-plus"; dr_mode = "drd";