From 3b86e48fbd5284a99b29df720c05fa8c45d231fc Mon Sep 17 00:00:00 2001 From: Tony Truong Date: Wed, 12 Feb 2020 12:06:06 -0800 Subject: [PATCH] ARM: dts: msm: update PCIe0 and PCIe1 PHY for lahaina v1 Update PCIe0 PHY to v0.92.1 and PCIe1 PHY to v1.03.1 based on H/W recommendation for Lahaina v1. Change-Id: Iff537fa8cee4791052be95318f6acb612aa2453c --- qcom/lahaina-pcie.dtsi | 21 ++++++++++++++++----- 1 file changed, 16 insertions(+), 5 deletions(-) diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi index 120a97ba..1d9555f0 100644 --- a/qcom/lahaina-pcie.dtsi +++ b/qcom/lahaina-pcie.dtsi @@ -106,7 +106,7 @@ qcom,slv-addr-space-size = <0x4000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <0>; + qcom,pcie-phy-ver = <10921>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -157,9 +157,10 @@ 0x06a8 0x0f 0x0 0x0048 0x90 0x0 0x0620 0xc1 0x0 - 0x0388 0x88 0x0 + 0x0388 0xa8 0x0 0x0398 0x0b 0x0 0x02dc 0x0d 0x0 + 0x10b0 0x18 0x0 0x0200 0x00 0x0 0x0244 0x03 0x0>; @@ -305,7 +306,7 @@ qcom,slv-addr-space-size = <0x20000000>; qcom,ep-latency = <10>; - qcom,pcie-phy-ver = <0>; + qcom,pcie-phy-ver = <11031>; qcom,phy-status-offset = <0x214>; qcom,phy-status-bit = <6>; qcom,phy-power-down-offset = <0x240>; @@ -354,8 +355,8 @@ 0x1400 0x02 0x0 0x1404 0x01 0x0 0x1408 0x01 0x0 - 0x0ee4 0x02 0x0 - 0x16e4 0x20 0x0 + 0x0ee4 0x00 0x0 + 0x16e4 0x00 0x0 0x115c 0xff 0x0 0x1160 0xbf 0x0 0x1164 0xbf 0x0 @@ -366,6 +367,16 @@ 0x1964 0xbf 0x0 0x1968 0x7f 0x0 0x196c 0xc8 0x0 + 0x1170 0xb4 0x0 + 0x1174 0x7b 0x0 + 0x1178 0x5c 0x0 + 0x117c 0xdc 0x0 + 0x1180 0xdc 0x0 + 0x1970 0xb4 0x0 + 0x1974 0x7b 0x0 + 0x1978 0x5c 0x0 + 0x197c 0xdc 0x0 + 0x1980 0xdc 0x0 0x02dc 0x05 0x0 0x0388 0x88 0x0 0x0398 0x0b 0x0