From 3bffda3c88488a9ae249b59b5a0747c8273646d4 Mon Sep 17 00:00:00 2001 From: Sachin Gupta Date: Tue, 14 Jun 2022 15:37:26 +0530 Subject: [PATCH] ARM: dts: msm: Add eMMC and SD card support for ravelin Add eMMC & SD card support for ravelin rumi. Change-Id: Ibed248d82b30daaa24e0644f8676a5a3c05a5b72 --- qcom/ravelin-pinctrl.dtsi | 102 ++++++++++++++++++++++++++++++++++++++ qcom/ravelin-rumi.dtsi | 43 ++++++++++++++++ qcom/ravelin.dtsi | 96 +++++++++++++++++++++++++++++++++++ 3 files changed, 241 insertions(+) diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi index 62025d55..d28db4ab 100644 --- a/qcom/ravelin-pinctrl.dtsi +++ b/qcom/ravelin-pinctrl.dtsi @@ -49,5 +49,107 @@ }; }; }; + + sdc1_on: sdc1_on { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <10>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc1_off: sdc1_off { + clk { + pins = "sdc1_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc1_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc1_data"; + bias-pull-up; + drive-strength = <2>; + }; + + rclk { + pins = "sdc1_rclk"; + bias-pull-down; + }; + }; + + sdc2_on: sdc2_on { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <16>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <10>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <10>; + }; + + sd-cd { + pins = "gpio101"; + bias-pull-up; + drive-strength = <2>; + }; + }; + + sdc2_off: sdc2_off { + clk { + pins = "sdc2_clk"; + bias-disable; + drive-strength = <2>; + }; + + cmd { + pins = "sdc2_cmd"; + bias-pull-up; + drive-strength = <2>; + }; + + data { + pins = "sdc2_data"; + bias-pull-up; + drive-strength = <2>; + }; + + sd-cd { + pins = "gpio101"; + bias-pull-up; + drive-strength = <2>; + }; + }; }; }; diff --git a/qcom/ravelin-rumi.dtsi b/qcom/ravelin-rumi.dtsi index 9666eeac..52c6d43f 100644 --- a/qcom/ravelin-rumi.dtsi +++ b/qcom/ravelin-rumi.dtsi @@ -1,4 +1,5 @@ #include +#include &soc { timer { @@ -104,6 +105,48 @@ status = "ok"; }; +&sdhc_1 { + status = "ok"; + vdd-supply = <&L5E>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 570000>; + + vdd-io-supply = <&L19B>; + qcom,vdd-io-always-on; + qcom,vdd-io-lpm-sup; + qcom,vdd-io-voltage-level = <1800000 1800000>; + qcom,vdd-io-current-level = <0 325000>; + + /delete-property/ mmc-ddr-1_8v; + /delete-property/ mmc-hs200-1_8v; + /delete-property/ mmc-hs400-1_8v; + /delete-property/ mmc-hs400-enhanced-strobe; + max-frequency = <100000000>; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc1_on>; + pinctrl-1 = <&sdc1_off>; +}; + +&sdhc_2 { + status = "ok"; + vdd-supply = <&L24B>; + qcom,vdd-voltage-level = <2960000 2960000>; + qcom,vdd-current-level = <0 800000>; + + vdd-io-supply = <&L28B>; + qcom,vdd-io-voltage-level = <2960000 2960000>; + qcom,vdd-io-current-level = <0 22000>; + + is_rumi; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&sdc2_on>; + pinctrl-1 = <&sdc2_off>; + + cd-gpios = <&tlmm 101 GPIO_ACTIVE_LOW>; +}; + &gcc { clocks = <&bi_tcxo>, <&sleep_clk>, <&pcie_0_pipe_clk>, <&ufs_phy_rx_symbol_0_clk>, diff --git a/qcom/ravelin.dtsi b/qcom/ravelin.dtsi index fb02642a..f9379548 100644 --- a/qcom/ravelin.dtsi +++ b/qcom/ravelin.dtsi @@ -28,6 +28,8 @@ aliases { serial0 = &qupv3_se2_2uart; ufshc1 = &ufshc_mem; /* Embedded UFS Slot */ + mmc0 = &sdhc_1; /*SDC1 eMMC slot*/ + mmc1 = &sdhc_2; /* SDC2 SD card slot */ }; firmware: firmware {}; @@ -753,6 +755,100 @@ }; }; + sdhc_1: sdhci@7C4000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x007C4000 0x1000>, <0x007C5000 0x1000>; + reg-names = "hc", "cqhci"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <8>; + non-removable; + supports-cqe; + + no-sd; + no-sdio; + + mmc-ddr-1_8v; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + mmc-hs400-enhanced-strobe; + + cap-mmc-hw-reset; + + clocks = <&gcc GCC_SDCC1_AHB_CLK>, + <&gcc GCC_SDCC1_APPS_CLK>, + <&gcc GCC_SDCC1_ICE_CORE_CLK>; + clock-names = "iface", "core", "ice_core"; + + qcom,ice-clk-rates = <300000000 100000000>; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x000F642C 0x0 0x01 + 0x2C010800 0x80040868>; + + /* Add dt entry for gcc hw reset */ + resets = <&gcc GCC_SDCC1_BCR>; + reset-names = "core_reset"; + + iommus = <&apps_smmu 0x560 0x0>; + dma-coherent; + qcom,iommu-dma = "bypass"; + + qos0 { + mask = <0x03>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + + sdhc_2: sdhci@8804000 { + status = "disabled"; + + compatible = "qcom,sdhci-msm-v5"; + reg = <0x08804000 0x1000>; + reg-names = "hc"; + + interrupts = , + ; + interrupt-names = "hc_irq", "pwr_irq"; + + bus-width = <4>; + no-sdio; + no-mmc; + qcom,restore-after-cx-collapse; + + clocks = <&gcc GCC_SDCC2_AHB_CLK>, + <&gcc GCC_SDCC2_APPS_CLK>; + clock-names = "iface", "core"; + + /* DLL HSR settings. Refer go/hsr - DLL settings */ + qcom,dll-hsr-list = <0x0007642C 0x0 0x10 + 0x2C010800 0x80040868>; + + iommus = <&apps_smmu 0x140 0x0>; + dma-coherent; + qcom,iommu-dma = "bypass"; + + qos0 { + mask = <0x03>; + vote = <44>; + }; + + qos1 { + mask = <0x3f>; + vote = <44>; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc";