From 3e9d32505f182de55376fdc998dd78ecec153573 Mon Sep 17 00:00:00 2001
From: Yatish Kumar Singh <yatishku@qti.qualcomm.com>
Date: Mon, 2 May 2022 15:06:00 +0530
Subject: [PATCH] ARM: dts: msm: Add QUPv3 UART console node for anorak

Enable console support on anorak

Change-Id: I9a75d83ff55580b33981d2fb28fcfe3c01c292cb
---
 qcom/anorak-pinctrl.dtsi | 26 ++++++++++++++++++++++++++
 qcom/anorak-qupv3.dtsi   | 39 +++++++++++++++++++++++++++++++++++++++
 qcom/anorak-rumi.dtsi    |  4 ++++
 qcom/anorak.dtsi         |  6 ++++++
 4 files changed, 75 insertions(+)
 create mode 100644 qcom/anorak-qupv3.dtsi

diff --git a/qcom/anorak-pinctrl.dtsi b/qcom/anorak-pinctrl.dtsi
index 4d1f6044..ed529d39 100644
--- a/qcom/anorak-pinctrl.dtsi
+++ b/qcom/anorak-pinctrl.dtsi
@@ -1,3 +1,29 @@
 &tlmm {
+	qupv3_se6_2uart_pins: qupv3_se6_2uart_pins {
+		qupv3_se6_2uart_active: qupv3_se6_2uart_active {
+			mux {
+				pins = "gpio156", "gpio157";
+				function = "qup0_se6";
+			};
 
+			config {
+				pins = "gpio156", "gpio157";
+				drive-strength= <2>;
+				bias-disable;
+			};
+		};
+
+		qupv3_se6_2uart_sleep: qupv3_se6_2uart_sleep {
+			mux {
+				pins = "gpio156", "gpio157";
+				function = "gpio";
+			};
+
+			config {
+				pins = "gpio156", "gpio157";
+				drive-strength = <2>;
+				bias-pull-down;
+			};
+		};
+	};
 };
diff --git a/qcom/anorak-qupv3.dtsi b/qcom/anorak-qupv3.dtsi
new file mode 100644
index 00000000..e352c2ba
--- /dev/null
+++ b/qcom/anorak-qupv3.dtsi
@@ -0,0 +1,39 @@
+&soc {
+	/* QUPv3_0  wrapper  instance */
+	qupv3_0: qcom,qupv3_0_geni_se@9c0000 {
+		compatible = "qcom,qupv3-geni-se";
+		reg = <0x9c0000 0x2000>;
+		qcom,msm-bus,num-paths = <3>;
+		interconnect-names = "qup-core", "snoc-llcc", "qup-ddr";
+		interconnects =
+		<&clk_virt MASTER_QUP_CORE_0 &clk_virt SLAVE_QUP_CORE_0>,
+		<&system_noc MASTER_A2NOC_SNOC &gem_noc SLAVE_LLCC>,
+		<&aggre2_noc MASTER_QUP_0 &mc_virt SLAVE_EBI1>;
+		/*
+		 * iommus = <&apps_smmu 0x5a3 0x0>;
+		 * qcom,iommu-dma-addr-pool = <0x40000000 0x10000000>;
+		 * qcom,iommu-geometry = <0x40000000 0x10000000>;
+		 * qcom,iommu-dma = "fastmap";
+		 * dma-coherent;
+		 */
+		status = "ok";
+	};
+
+	/* Debug UART Instance */
+	qupv3_se6_2uart: qcom,qup_uart@998000 {
+		compatible = "qcom,msm-geni-console";
+		reg = <0x998000 0x4000>;
+		reg-names = "se_phys";
+		interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>;
+		clock-names = "se-clk", "m-ahb", "s-ahb";
+		clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>,
+			<&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>;
+		pinctrl-names = "default", "sleep";
+		pinctrl-0 = <&qupv3_se6_2uart_active>;
+		pinctrl-1 = <&qupv3_se6_2uart_sleep>;
+		qcom,wrapper-core = <&qupv3_0>;
+		status = "disabled";
+	};
+};
+
diff --git a/qcom/anorak-rumi.dtsi b/qcom/anorak-rumi.dtsi
index 34307f2d..b34f5506 100644
--- a/qcom/anorak-rumi.dtsi
+++ b/qcom/anorak-rumi.dtsi
@@ -89,6 +89,10 @@
 
 };
 
+&qupv3_se6_2uart {
+	qcom,rumi_platform;
+};
+
 &gcc {
 	clocks = <&bi_tcxo>, <&sleep_clk>,
 		<&pcie_0_pipe_clk>, <&pcie_1_pipe_clk>,
diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi
index a385528c..20209619 100644
--- a/qcom/anorak.dtsi
+++ b/qcom/anorak.dtsi
@@ -31,6 +31,7 @@
 
 	aliases {
 		ufshc1 = &ufshc_mem; /* Embedded UFS Slot */
+		serial0 = &qupv3_se6_2uart;
 	};
 
 	cpus {
@@ -844,8 +845,13 @@
 	};
 };
 
+#include "anorak-qupv3.dtsi"
 #include "diwali-gdsc.dtsi"
 
+&qupv3_se6_2uart {
+	status = "ok";
+};
+
 &cam_cc_bps_gdsc {
 	clocks = <&gcc GCC_CAMERA_AHB_CLK>;
 	clock-names = "ahb_clk";