From 2d131b077784dd5ab1c10929978e7582bd5f811e Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Sat, 4 Dec 2021 12:57:46 +0530 Subject: [PATCH 1/2] dt-bindings: Add bindings for Anorak SoC Add bindings to msm documentation for Anorak SoC. Change-Id: I2e8113d4a182405a75bece041a3f9cb3e87c93bc --- bindings/arm/msm/msm.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/bindings/arm/msm/msm.txt b/bindings/arm/msm/msm.txt index 554ac590..6eddd8e2 100644 --- a/bindings/arm/msm/msm.txt +++ b/bindings/arm/msm/msm.txt @@ -101,6 +101,9 @@ SoCs: - PARROT compatible = "qcom,parrot" +- ANORAK + compatible = "qcom,anorak" + Generic board variants: - CDP device: @@ -283,3 +286,5 @@ compatible = "qcom,diwalip-qrd" compatible = "qcom,diwalip-atp" compatible = "qcom,neo-rumi" compatible = "qcom,parrot-rumi" +compatible = "qcom,anorak-rumi" +compatible = "qcom,anorak-idp" From 10c1375212300a50b17622dcaeb007d3c3f07025 Mon Sep 17 00:00:00 2001 From: Sahitya Tummala Date: Sat, 4 Dec 2021 13:00:41 +0530 Subject: [PATCH 2/2] ARM: dts: msm: Add initial device tree for Anorak Add initial device tree for Anorak SoC and RUMI platforms. Change-Id: I80b772883a03649118621c4dcbab8d3023ff84fb --- qcom/Makefile | 7 ++ qcom/anorak-rumi-overlay.dts | 12 ++ qcom/anorak-rumi.dts | 11 ++ qcom/anorak-rumi.dtsi | 15 +++ qcom/anorak.dts | 9 ++ qcom/anorak.dtsi | 231 +++++++++++++++++++++++++++++++++++ 6 files changed, 285 insertions(+) create mode 100644 qcom/anorak-rumi-overlay.dts create mode 100644 qcom/anorak-rumi.dts create mode 100644 qcom/anorak-rumi.dtsi create mode 100644 qcom/anorak.dts create mode 100644 qcom/anorak.dtsi diff --git a/qcom/Makefile b/qcom/Makefile index 8f17a8d1..40a64feb 100644 --- a/qcom/Makefile +++ b/qcom/Makefile @@ -344,6 +344,13 @@ dtb-$(CONFIG_ARCH_SM8150) += sm8150-cdp.dtb \ endif endif +ifeq ($(CONFIG_BUILD_ARM64_DT_OVERLAY),y) +dtbo-$(CONFIG_ARCH_ANORAK) += anorak-rumi-overlay.dtbo +anorak-rumi-overlay.dtbo-base := anorak.dtb +else +dtb-$(CONFIG_ARCH_ANORAK) += anorak-rumi.dtb +endif + ifeq ($(CONFIG_ARCH_LAHAINA), y) ifeq ($(CONFIG_ARCH_QTI_VM), y) dtb-$(CONFIG_ARCH_QTI_VM) += lahaina-vm-mtp.dtb \ diff --git a/qcom/anorak-rumi-overlay.dts b/qcom/anorak-rumi-overlay.dts new file mode 100644 index 00000000..c419e2e2 --- /dev/null +++ b/qcom/anorak-rumi-overlay.dts @@ -0,0 +1,12 @@ +/dts-v1/; +/plugin/; + +#include "anorak.dtsi" +#include "anorak-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Anorak RUMI"; + compatible = "qcom,anorak-rumi", "qcom,anorak", "qcom,rumi"; + qcom,msm-id = <549 0x10000>; + qcom,board-id = <0xF 0x0>; +}; diff --git a/qcom/anorak-rumi.dts b/qcom/anorak-rumi.dts new file mode 100644 index 00000000..4e29e2b3 --- /dev/null +++ b/qcom/anorak-rumi.dts @@ -0,0 +1,11 @@ +/dts-v1/; +/memreserve/ 0x90000000 0x00010000; + +#include "anorak.dtsi" +#include "anorak-rumi.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Anorak RUMI"; + compatible = "qcom,anorak-rumi", "qcom,anorak", "qcom,rumi"; + qcom,board-id = <0xF 0x0>; +}; diff --git a/qcom/anorak-rumi.dtsi b/qcom/anorak-rumi.dtsi new file mode 100644 index 00000000..2865ab86 --- /dev/null +++ b/qcom/anorak-rumi.dtsi @@ -0,0 +1,15 @@ +&chosen { + bootargs = "nokaslr kpti=0 log_buf_len=256K swiotlb=0 loop.max_part=7"; +}; + +&arch_timer { + clock-frequency = <500000>; +}; + +&memtimer { + clock-frequency = <500000>; +}; + +&soc { + +}; diff --git a/qcom/anorak.dts b/qcom/anorak.dts new file mode 100644 index 00000000..9badc9de --- /dev/null +++ b/qcom/anorak.dts @@ -0,0 +1,9 @@ +/dts-v1/; + +#include "anorak.dtsi" + +/ { + model = "Qualcomm Technologies, Inc. Anorak SoC"; + compatible = "qcom,anorak"; + qcom,board-id = <0 0>; +}; diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi new file mode 100644 index 00000000..8cd0cba1 --- /dev/null +++ b/qcom/anorak.dtsi @@ -0,0 +1,231 @@ +#include + +/ { + model = "Qualcomm Technologies, Inc. Anorak"; + compatible = "qcom,anorak"; + qcom,msm-id = <549 0x10000>; + interrupt-parent = <&intc>; + + #address-cells = <2>; + #size-cells = <2>; + memory { device_type = "memory"; reg = <0 0 0 0>; }; + + + chosen: chosen { }; + + aliases { }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + CPU0: cpu@0 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x0>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_0>; + L2_0: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + + L3_0: l3-cache { + compatible = "arm,arch-cache"; + cache-level = <3>; + }; + }; + }; + + CPU1: cpu@100 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x100>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_1>; + L2_1: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + }; + + CPU2: cpu@200 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x200>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_2>; + L2_2: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU3: cpu@300 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x300>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_3>; + L2_3: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + + }; + + CPU4: cpu@400 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x400>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_4>; + L2_4: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + CPU5: cpu@500 { + device_type = "cpu"; + compatible = "qcom,kryo"; + reg = <0x0 0x500>; + enable-method = "spin-table"; + cpu-release-addr = <0x0 0x90000000>; + next-level-cache = <&L2_5>; + L2_5: l2-cache { + compatible = "arm,arch-cache"; + cache-level = <2>; + next-level-cache = <&L3_0>; + }; + }; + + cpu-map { + cluster0 { + core0 { + cpu = <&CPU0>; + }; + + core1 { + cpu = <&CPU1>; + }; + }; + + cluster1 { + core0 { + cpu = <&CPU2>; + }; + + core1 { + cpu = <&CPU3>; + }; + + core2 { + cpu = <&CPU4>; + }; + + core3 { + cpu = <&CPU5>; + }; + }; + }; + }; + + soc: soc { }; +}; + +&soc { + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0 0xffffffff>; + compatible = "simple-bus"; + + intc: interrupt-controller@17200000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <3>; + interrupt-controller; + #redistributor-regions = <1>; + redistributor-stride = <0x0 0x20000>; + reg = <0x17200000 0x10000>, /* GICD */ + <0x17260000 0x100000>; /* GICR * 8 */ + interrupts = ; + }; + + arch_timer: timer { + compatible = "arm,armv8-timer"; + interrupts = , + , + , + ; + clock-frequency = <19200000>; + }; + + memtimer: timer@17420000 { + #address-cells = <1>; + #size-cells = <1>; + ranges; + compatible = "arm,armv7-timer-mem"; + reg = <0x17420000 0x1000>; + clock-frequency = <19200000>; + + frame@17421000 { + frame-number = <0>; + interrupts = , + ; + reg = <0x17421000 0x1000>, + <0x17422000 0x1000>; + }; + + frame@17423000 { + frame-number = <1>; + interrupts = ; + reg = <0x17423000 0x1000>; + status = "disabled"; + }; + + frame@17425000 { + frame-number = <2>; + interrupts = ; + reg = <0x17425000 0x1000>; + status = "disabled"; + }; + + frame@17427000 { + frame-number = <3>; + interrupts = ; + reg = <0x17427000 0x1000>; + status = "disabled"; + }; + + frame@17429000 { + frame-number = <4>; + interrupts = ; + reg = <0x17429000 0x1000>; + status = "disabled"; + }; + + frame@1742b000 { + frame-number = <5>; + interrupts = ; + reg = <0x1742b000 0x1000>; + status = "disabled"; + }; + + frame@1742d000 { + frame-number = <6>; + interrupts = ; + reg = <0x1742d000 0x1000>; + status = "disabled"; + }; + }; +};