From 407632aae623ef507f50a0db552cb3bb96cf2109 Mon Sep 17 00:00:00 2001
From: Mohammed Mirza Mandayappurath Manzoor <mmandaya@quicinc.com>
Date: Tue, 6 Jul 2021 14:24:33 -0700
Subject: [PATCH] ARM: dts: msm: Add higher power levels and ACD configurations
 for c500 v2

c500 v2 supports additional higher gpu power levels. Also add ACD control
register configurations that contain the DVM values for ACD throttling.

Change-Id: Ifbee5158ec2c97d5087049fe37acf10ce8477667
---
 qcom/waipio-v2-gpu.dtsi | 70 ++++++++++++++++++++++++++++++++---------
 1 file changed, 55 insertions(+), 15 deletions(-)

diff --git a/qcom/waipio-v2-gpu.dtsi b/qcom/waipio-v2-gpu.dtsi
index 608f0576..7853d5de 100644
--- a/qcom/waipio-v2-gpu.dtsi
+++ b/qcom/waipio-v2-gpu.dtsi
@@ -2,7 +2,7 @@
 
 	compatible = "qcom,adreno-gpu-c500v2", "qcom,kgsl-3d0";
 
-	qcom,initial-pwrlevel = <7>;
+	qcom,initial-pwrlevel = <9>;
 
 	qcom,gpu-model = "Adreno730v2";
 
@@ -14,82 +14,122 @@
 
 		qcom,gpu-pwrlevel@0 {
 			reg = <0>;
+			qcom,gpu-freq = <818000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_TURBO>;
+
+			qcom,bus-freq = <10>;
+			qcom,bus-min = <10>;
+			qcom,bus-max = <10>;
+
+			qcom,acd-level = <0x882c5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@1 {
+			reg = <1>;
+			qcom,gpu-freq = <791000000>;
+			qcom,level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
+
+			qcom,bus-freq = <10>;
+			qcom,bus-min = <9>;
+			qcom,bus-max = <10>;
+
+			qcom,acd-level = <0x882c5ffd>;
+		};
+
+		qcom,gpu-pwrlevel@2 {
+			reg = <2>;
 			qcom,gpu-freq = <734000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_NOM>;
 
 			qcom,bus-freq = <10>;
 			qcom,bus-min = <9>;
 			qcom,bus-max = <10>;
+
+			qcom,acd-level = <0x882d5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@1 {
-			reg = <1>;
+		qcom,gpu-pwrlevel@3 {
+			reg = <3>;
 			qcom,gpu-freq = <640000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L2>;
 
 			qcom,bus-freq = <10>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <10>;
+
+			qcom,acd-level = <0xa82d5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@2 {
-			reg = <2>;
+		qcom,gpu-pwrlevel@4 {
+			reg = <4>;
 			qcom,gpu-freq = <599000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 
 			qcom,bus-freq = <8>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <9>;
+
+			qcom,acd-level = <0x882e5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@3 {
-			reg = <3>;
+		qcom,gpu-pwrlevel@5 {
+			reg = <5>;
 			qcom,gpu-freq = <545000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS_L0>;
 
 			qcom,bus-freq = <8>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <9>;
+
+			qcom,acd-level = <0x882e5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@4 {
-			reg = <4>;
+		qcom,gpu-pwrlevel@6 {
+			reg = <6>;
 			qcom,gpu-freq = <492000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_SVS>;
 
 			qcom,bus-freq = <6>;
 			qcom,bus-min = <6>;
 			qcom,bus-max = <8>;
+
+			qcom,acd-level = <0x882e5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@5 {
-			reg = <5>;
+		qcom,gpu-pwrlevel@7 {
+			reg = <7>;
 			qcom,gpu-freq = <421000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>;
 
 			qcom,bus-freq = <6>;
 			qcom,bus-min = <3>;
 			qcom,bus-max = <8>;
+
+			qcom,acd-level = <0xa82e5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@6 {
-			reg = <6>;
+		qcom,gpu-pwrlevel@8 {
+			reg = <8>;
 			qcom,gpu-freq = <350000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 
 			qcom,bus-freq = <3>;
 			qcom,bus-min = <1>;
 			qcom,bus-max = <5>;
+
+			qcom,acd-level = <0x882f5ffd>;
 		};
 
-		qcom,gpu-pwrlevel@7 {
-			reg = <7>;
+		qcom,gpu-pwrlevel@9 {
+			reg = <9>;
 			qcom,gpu-freq = <285000000>;
 			qcom,level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>;
 
 			qcom,bus-freq = <2>;
 			qcom,bus-min = <1>;
 			qcom,bus-max = <5>;
+
+			qcom,acd-level = <0x882f5ffd>;
 		};
 	};
 };