From 89395dde2295f15ac301037765284734451de5c4 Mon Sep 17 00:00:00 2001
From: Uttkarsh Aggarwal <uaggarwa@qti.qualcomm.com>
Date: Tue, 22 Nov 2022 17:50:04 +0530
Subject: [PATCH] ARM: dts: msm: Adding pin configuration for USB3 PHY
 portselect on Ravelin

TLMM pin 94 is used to notify the USB3/DP Combo PHY of the
orientation in which the USB type-C connection is detected.
Select this pinctrl from the usb_qmp_dp_phy device and ensure
it is selecting the "usb0_phy_ps" pin function for Ravelin.

Change-Id: Iaeac6a9add144f3b862a7d9549693c087647706f
---
 qcom/ravelin-pinctrl.dtsi | 15 +++++++++++++++
 qcom/ravelin-usb.dtsi     |  3 +++
 2 files changed, 18 insertions(+)

diff --git a/qcom/ravelin-pinctrl.dtsi b/qcom/ravelin-pinctrl.dtsi
index 686fe9ff..d8bbd6aa 100644
--- a/qcom/ravelin-pinctrl.dtsi
+++ b/qcom/ravelin-pinctrl.dtsi
@@ -1425,5 +1425,20 @@
 				};
 			};
 		};
+
+		usb_phy_ps: usb_phy_ps {
+			usb3phy_portselect_default: usb3phy_portselect_default {
+				mux {
+					pins = "gpio94";
+					function = "usb0_phy_ps";
+				};
+
+				config {
+					pins = "gpio94";
+					bias-disable;
+					drive-strength = <2>;
+				};
+			};
+		};
 	};
 };
diff --git a/qcom/ravelin-usb.dtsi b/qcom/ravelin-usb.dtsi
index f1230875..6830f4c2 100644
--- a/qcom/ravelin-usb.dtsi
+++ b/qcom/ravelin-usb.dtsi
@@ -124,6 +124,9 @@
 			<&gcc GCC_USB3_PHY_PRIM_BCR>;
 		reset-names = "global_phy_reset", "phy_reset";
 
+		pinctrl-names = "default";
+		pinctrl-0 = <&usb3phy_portselect_default>;
+
 		qcom,qmp-phy-reg-offset =
 			<USB3_DP_PCS_PCS_STATUS1
 			USB3_DP_PCS_USB3_AUTONOMOUS_MODE_CTRL