From 1e449708f3c27186eacccc44a390bc6ac09eea6c Mon Sep 17 00:00:00 2001 From: Jaskaran Singh Date: Tue, 25 Jan 2022 12:01:13 +0530 Subject: [PATCH] ARM: dts: msm: Add clock regulator nodes for gfx smmu on neo Add clock regulator nodes for gfx smmu on neo. Change-Id: I986ea45a27aa3d4ffd578cb3cddde47c54d0dfc7 --- qcom/msm-arm-smmu-neo.dtsi | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/qcom/msm-arm-smmu-neo.dtsi b/qcom/msm-arm-smmu-neo.dtsi index 74577ddb..4dfcc9e3 100644 --- a/qcom/msm-arm-smmu-neo.dtsi +++ b/qcom/msm-arm-smmu-neo.dtsi @@ -18,6 +18,23 @@ ranges; dma-coherent; + qcom,regulator-names = "vdd"; + vdd-supply = <&gpu_cc_cx_gdsc>; + + clocks = <&gpucc GPU_CC_CX_GMU_CLK>, + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&gcc GCC_GPU_MEMNOC_GFX_CLK>, + <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, + <&gpucc GPU_CC_AHB_CLK>; + clock-names = + "gpu_cc_cx_gmu", + "gpu_cc_hub_cx_int", + "gpu_cc_hlos1_vote_gpu_smmu", + "gcc_gpu_memnoc_gfx", + "gcc_gpu_snoc_dvm_gfx", + "gpu_cc_ahb"; + qcom,actlr = /* All CBs of GFX: +15 deep PF */ <0x000 0x3ff 0x32B>,