From 9844984a797c3d4588bfd03179448ef409b6e529 Mon Sep 17 00:00:00 2001 From: Elson Roy Serrao Date: Wed, 1 Apr 2020 11:41:05 -0700 Subject: [PATCH] ARM: dts: msm: Increase the dwc3 reg address range for Lahaina The register address range for Lahaina is not covering all the controller registers. Tuning the Tx deemph registers for dwc3 gen2 protocol test is not possible with the current range. Modify the reg property to cover the entire range as defined in the data book to fix this issue. Change-Id: I34b605f920af7cae8b2efd69a54f96e8cde5c001 --- qcom/lahaina-usb.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/qcom/lahaina-usb.dtsi b/qcom/lahaina-usb.dtsi index 7ef5e8bc..0344eca0 100644 --- a/qcom/lahaina-usb.dtsi +++ b/qcom/lahaina-usb.dtsi @@ -56,7 +56,7 @@ dwc3@a600000 { compatible = "snps,dwc3"; - reg = <0xa600000 0xcd00>; + reg = <0xa600000 0xd93c>; interrupts = ; usb-phy = <&usb2_phy0>, <&usb_qmp_dp_phy>; linux,sysdev_is_parent; @@ -376,7 +376,7 @@ dwc3@a800000 { compatible = "snps,dwc3"; - reg = <0xa800000 0xcd00>; + reg = <0xa800000 0xd93c>; interrupts = ; usb-phy = <&usb2_phy1>, <&usb_qmp_phy>; linux,sysdev_is_parent;