From 4ce97d3889f73e20010ff96423c137bf9cba6bbd Mon Sep 17 00:00:00 2001
From: Tony Truong <truong@quicinc.com>
Date: Tue, 28 Apr 2020 17:05:44 -0700
Subject: [PATCH] ARM: dts: msm: add entry for PCIe0 to manage PCIe PHY PLL on
 lahaina

PCIe0 needs to manage PHY PLL on lahaina. Therefore add the DT
entries so that PCIe0 has to correct information to support this
request.

Change-Id: I622b4d3dc24e530554c23cbeeb0ee6dd528e5587
---
 qcom/lahaina-pcie.dtsi | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/qcom/lahaina-pcie.dtsi b/qcom/lahaina-pcie.dtsi
index 85c0eac3..ecabac66 100644
--- a/qcom/lahaina-pcie.dtsi
+++ b/qcom/lahaina-pcie.dtsi
@@ -109,6 +109,11 @@
 		qcom,slv-addr-space-size = <0x4000000>;
 		qcom,ep-latency = <10>;
 
+		qcom,phy-manage-pll = <1>;
+		qcom,phy-resetsm-cntrl2 = <0xa0>;
+		qcom,phy-core-pll-en-mux = <7>;
+		qcom,phy-c-ready-status = <0x178>;
+
 		qcom,pcie-phy-ver = <10971>;
 		qcom,phy-status-offset = <0x214>;
 		qcom,phy-status-bit = <6>;