From 51e92a8bda8b100f62a0fb8ad3c34aaea226fea1 Mon Sep 17 00:00:00 2001
From: Vivek Pernamitta <vpernami@qti.qualcomm.com>
Date: Wed, 18 May 2022 17:43:11 +0530
Subject: [PATCH] ARM: dts: msm:  Vote CX level to SVS for PCIe GEN-3 speed

Vote CX level to SVS for PCIe GEN3 speed instead of NOM.

Change-Id: I6694bda61515b0fd48bad5e00ee3508b838d1e44
---
 qcom/diwali-pcie.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/qcom/diwali-pcie.dtsi b/qcom/diwali-pcie.dtsi
index 5ebf3939..55df1593 100644
--- a/qcom/diwali-pcie.dtsi
+++ b/qcom/diwali-pcie.dtsi
@@ -66,8 +66,8 @@
 				RPMH_REGULATOR_LEVEL_LOW_SVS
 				19200000
 				/* Gen3 */
-				RPMH_REGULATOR_LEVEL_NOM
-				RPMH_REGULATOR_LEVEL_NOM
+				RPMH_REGULATOR_LEVEL_SVS
+				RPMH_REGULATOR_LEVEL_SVS
 				100000000>;
 
 		interconnect-names = "icc_path";