From 52a08e91999981acf3fc659a238da06ddd0bfb96 Mon Sep 17 00:00:00 2001 From: Taniya Das Date: Mon, 6 Apr 2020 15:19:40 +0530 Subject: [PATCH] ARM: dts: msm: Update the RPMHCC node for SHIMA Update the RPMHCC node to use the RPMH clock driver and move the dummy rpmhcc to RUMI. Change-Id: If26c8457ad61c2e7b205885d80650b9933ee73f5 --- qcom/shima-rumi.dtsi | 21 +++++++++++++++++++++ qcom/shima.dtsi | 28 +++++----------------------- 2 files changed, 26 insertions(+), 23 deletions(-) diff --git a/qcom/shima-rumi.dtsi b/qcom/shima-rumi.dtsi index 7a012a61..5f748583 100644 --- a/qcom/shima-rumi.dtsi +++ b/qcom/shima-rumi.dtsi @@ -25,6 +25,22 @@ 0x10060 0x3c 0x0 0x4>; }; + + bi_tcxo: bi_tcxo { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; + + bi_tcxo_ao: bi_tcxo_ao { + compatible = "fixed-factor-clock"; + clock-mult = <1>; + clock-div = <2>; + clocks = <&xo_board>; + #clock-cells = <0>; + }; }; &usb0 { @@ -34,3 +50,8 @@ dr_mode = "peripheral"; }; }; + +&rpmhcc { + compatible = "qcom,dummycc"; + clock-output-names = "rpmhcc_clocks"; +}; diff --git a/qcom/shima.dtsi b/qcom/shima.dtsi index f8f97707..3c5c6d76 100644 --- a/qcom/shima.dtsi +++ b/qcom/shima.dtsi @@ -486,22 +486,6 @@ }; }; - bi_tcxo: bi_tcxo { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <2>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - - bi_tcxo_ao: bi_tcxo_ao { - compatible = "fixed-factor-clock"; - clock-mult = <1>; - clock-div = <2>; - clocks = <&xo_board>; - #clock-cells = <0>; - }; - aopcc: qcom,aopcc { compatible = "qcom,dummycc"; clock-output-names = "aopcc_clocks"; @@ -509,13 +493,6 @@ #reset-cells = <1>; }; - rpmhcc: qcom,rpmhcc { - compatible = "qcom,dummycc"; - clock-output-names = "rpmhcc_clocks"; - #clock-cells = <1>; - #reset-cells = <1>; - }; - gcc: qcom,gcc@100000 { compatible = "qcom,dummycc"; clock-output-names = "gcc_clocks"; @@ -837,6 +814,11 @@ , , ; + + rpmhcc: qcom,rpmhclk { + compatible = "qcom,shima-rpmh-clk"; + #clock-cells = <1>; + }; }; disp_rsc: rsc@af20000 {