From 52ab54c85b62c1ddcf01526ba1a4773138d49b33 Mon Sep 17 00:00:00 2001 From: Liron Daniel Date: Sun, 17 Jan 2021 14:06:48 +0200 Subject: [PATCH] ARM: dts: qcom: Add SPU related nodes to waipio Needed for SPU pil on waipio. Change-Id: Ied93685b6987033cfe9a4373680f0af1f56c9562 --- bindings/remoteproc/qcom,spss.txt | 59 ++++++++++++++++++++ qcom/waipio.dtsi | 89 +++++++++++++++++++++++++++++++ 2 files changed, 148 insertions(+) create mode 100644 bindings/remoteproc/qcom,spss.txt diff --git a/bindings/remoteproc/qcom,spss.txt b/bindings/remoteproc/qcom,spss.txt new file mode 100644 index 00000000..0909197d --- /dev/null +++ b/bindings/remoteproc/qcom,spss.txt @@ -0,0 +1,59 @@ +Qualcomm Technologies, Inc. SPSS Peripheral Image Loader + +This document defines the binding for a component that loads and boots firmware +on the QTI Secure Processor. + +- compatible: + Usage: required + Value type: + Definition: must be one of: + "qcom,waipio-spss-pas" + +- reg: + Usage: required + Value type: + Definition: pairs of physical base addresses and region sizes of memory + mapped registers + +- reg-names: + Usage: required + Value type: + Definition: names of the registers defined by the 'reg' property above + +- interrupts: + Usage: required + Value type: + Definition: generic interrupt + +- clocks: + Usage: required + Value type: + Definition: reference to the xo clock and optionally aggre2 clock to be + held on behalf of the booting Hexagon core + +- clock-names: + Usage: required + Value type: + Definition: must be "xo" and optionally include "aggre2" + +- cx-supply: + Usage: required + Value type: + Definition: reference to the regulator to be held on behalf of the + booting Hexagon core + +- px-supply: + Usage: required + Value type: + Definition: reference to the px regulator to be held on behalf of the + booting Hexagon core + +- memory-region: + Usage: required + Value type: + Definition: reference to the reserved-memory for the ADSP + + += SUBNODES +The adsp node may have an subnode named "glink-edge" that describes the +communication edge, channels and devices related to the SPSS. \ No newline at end of file diff --git a/qcom/waipio.dtsi b/qcom/waipio.dtsi index 44d65dad..142123de 100644 --- a/qcom/waipio.dtsi +++ b/qcom/waipio.dtsi @@ -1138,6 +1138,95 @@ }; }; + /* PIL spss node - for loading Secure Processor */ + spss_pas: remoteproc-spss@1880000 { + compatible = "qcom,waipio-spss-pas"; + ranges; + reg = <0x188101c 0x4>, + <0x1881024 0x4>, + <0x1881028 0x4>, + <0x188103c 0x4>, + <0x1882014 0x4>; + reg-names = "sp2soc_irq_status", "sp2soc_irq_clr", + "sp2soc_irq_mask", "rmb_err", "rmb_err_spare2"; + interrupts = <0 352 1>; + + cx-supply = <&VDD_CX_LEVEL>; + cx-uV-uA = ; + px-supply = <&VDD_MXA_LEVEL>; + px-uV = ; + + clocks = <&clock_rpmh RPMH_CXO_CLK>; + clock-names = "xo"; + qcom,proxy-clock-names = "xo"; + status = "ok"; + + memory-region = <&spss_region_mem>; + qcom,spss-scsr-bits = <24 25>; + qcom,extra-size = <4096>; + + interconnects = <&aggre2_noc MASTER_CRYPTO &mc_virt SLAVE_EBI1>; + interconnect-names = "crypto_ddr"; + + glink-edge { + qcom,remote-pid = <8>; + mboxes = <&ipcc_mproc IPCC_CLIENT_SPSS + IPCC_MPROC_SIGNAL_GLINK_QMP>; + mbox-names = "spss_spss"; + interrupt-parent = <&ipcc_mproc>; + interrupts = ; + + reg = <0x1885008 0x8>, + <0x1885010 0x4>; + reg-names = "qcom,spss-addr", + "qcom,spss-size"; + + label = "spss"; + qcom,glink-label = "spss"; + }; + }; + + qcom,spcom { + compatible = "qcom,spcom"; + + qcom,rproc-handle = <&spss_pas>; + qcom,boot-enabled; + /* predefined channels, remote side is server */ + qcom,spcom-ch-names = "sp_kernel", "sp_ssr"; + /* sp2soc rmb shared register physical address and bmsk */ + qcom,spcom-sp2soc-rmb-reg-addr = <0x01881020>; + qcom,spcom-sp2soc-rmb-initdone-bit = <24>; + qcom,spcom-sp2soc-rmb-pbldone-bit = <25>; + /* soc2sp rmb shared register physical address */ + qcom,spcom-soc2sp-rmb-reg-addr = <0x01881030>; + qcom,spcom-soc2sp-rmb-sp-ssr-bit = <0>; + status = "ok"; + }; + + spss_utils: qcom,spss_utils { + compatible = "qcom,spss-utils"; + /* spss fuses physical address */ + qcom,rproc-handle = <&spss_pas>; + qcom,spss-fuse1-addr = <0x221C22EC>; + qcom,spss-fuse1-bit = <8>; + qcom,spss-fuse2-addr = <0x221C22EC>; + qcom,spss-fuse2-bit = <7>; + qcom,spss-fuse3-addr = <0x221C2238>; // IAR_FEATURE_ENABLED fuse + qcom,spss-fuse3-bit = <10>; + qcom,spss-fuse4-addr = <0x221C22EC>; // IAR_STATE fuse + qcom,spss-fuse4-bit = <21>; // 0x221C22EC bits 21-23 + qcom,spss-dev-firmware-name = "spss1d.mdt"; /* 8 chars max */ + qcom,spss-test-firmware-name = "spss1t.mdt"; /* 8 chars max */ + qcom,spss-prod-firmware-name = "spss1p.mdt"; /* 8 chars max */ + qcom,spss-debug-reg-addr = <0x01886020>; + qcom,spss-emul-type-reg-addr = <0x01fc8004>; + pil-mem = <&spss_region_mem>; + qcom,pil-size = <0x0F0000>; // padding to 960KB + status = "ok"; + }; + cache-controller@19200000 { compatible = "qcom,waipio-llcc", "qcom,llcc-v21"; reg = <0x19200000 0x580000> , <0x19A00000 0x80000>;