diff --git a/qcom/neo-thermal.dtsi b/qcom/neo-thermal.dtsi index d15d1076..c9a402fa 100644 --- a/qcom/neo-thermal.dtsi +++ b/qcom/neo-thermal.dtsi @@ -1,5 +1,9 @@ #include +&msm_gpu { + #cooling-cells = <2>; +}; + &soc { tsens0: thermal-sensor@c263000 { compatible = "qcom,tsens-v2"; @@ -11,6 +15,123 @@ interrupt-names = "uplow","critical"; #thermal-sensor-cells = <1>; }; + + qcom,cpu-pause { + compatible = "qcom,thermal-pause"; + + cpu0_pause: cpu0-pause { + qcom,cpus = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_pause: cpu1-pause { + qcom,cpus = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_pause: cpu2-pause { + qcom,cpus = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_pause: cpu3-pause { + qcom,cpus = <&CPU3>; + #cooling-cells = <2>; + }; + + /* Thermal-engine cooling devices */ + pause-cpu0 { + qcom,cpus = <&CPU0>; + qcom,cdev-alias = "pause-cpu0"; + }; + + pause-cpu1 { + qcom,cpus = <&CPU1>; + qcom,cdev-alias = "pause-cpu1"; + }; + + pause-cpu2 { + qcom,cpus = <&CPU2>; + qcom,cdev-alias = "pause-cpu2"; + }; + + pause-cpu3 { + qcom,cpus = <&CPU3>; + qcom,cdev-alias = "pause-cpu3"; + }; + }; + + qcom,cpu-hotplug { + compatible = "qcom,cpu-hotplug"; + + cpu0_hotplug: cpu0-hotplug { + qcom,cpu = <&CPU0>; + #cooling-cells = <2>; + }; + + cpu1_hotplug: cpu1-hotplug { + qcom,cpu = <&CPU1>; + #cooling-cells = <2>; + }; + + cpu2_hotplug: cpu2-hotplug { + qcom,cpu = <&CPU2>; + #cooling-cells = <2>; + }; + + cpu3_hotplug: cpu3-hotplug { + qcom,cpu = <&CPU3>; + #cooling-cells = <2>; + }; + }; + + thermal_ddr_freq_table: thermal-ddr-freq-table { + qcom,freq-tbl = < 2133000 >; + }; + + ddr_cdev: qcom,ddr-cdev { + compatible = "qcom,ddr-cooling-device"; + #cooling-cells = <2>; + qcom,freq-table = <&thermal_ddr_freq_table>; + qcom,bus-width = <4>; + interconnects = <&mc_virt MASTER_LLCC &mc_virt SLAVE_EBI1>; + }; + + qmi_tmd: qmi-tmd-devices { + compatible = "qcom,qmi-cooling-devices"; + cdsp { + qcom,instance-id = ; + + cdsp_sw: cdsp { + qcom,qmi-dev-name = "cdsp_sw"; + #cooling-cells = <2>; + }; + + cdsp_hw: cdsp_hw { + qcom,qmi-dev-name = "cdsp_hw"; + #cooling-cells = <2>; + }; + }; + }; + + qcom,cpufreq-cdev { + compatible = "qcom,cpufreq-cdev"; + qcom,cpus = <&CPU0>; + }; + + qcom,devfreq-cdev { + compatible = "qcom,devfreq-cdev"; + qcom,devfreq = <&msm_gpu>; + }; + + qcom,userspace-cdev { + compatible = "qcom,userspace-cooling-devices"; + + display_fps: display-fps { + qcom,max-level = <3>; + #cooling-cells = <2>; + }; + }; }; &thermal_zones { @@ -55,6 +176,12 @@ hysteresis = <5000>; type = "passive"; }; + + cpu0_emerg0: cpu0-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; }; }; @@ -80,6 +207,19 @@ hysteresis = <5000>; type = "passive"; }; + + cpu1_emerg0: cpu1-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu01_cdev { + trip = <&cpu1_emerg0>; + cooling-device = <&cpu1_pause 1 1>; + }; }; }; @@ -105,6 +245,19 @@ hysteresis = <5000>; type = "passive"; }; + + cpu2_emerg0: cpu2-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu02_cdev { + trip = <&cpu2_emerg0>; + cooling-device = <&cpu2_pause 1 1>; + }; }; }; @@ -130,6 +283,19 @@ hysteresis = <5000>; type = "passive"; }; + + cpu3_emerg0: cpu3-emerg0-cfg { + temperature = <110000>; + hysteresis = <10000>; + type = "passive"; + }; + }; + + cooling-maps { + cpu03_cdev { + trip = <&cpu3_emerg0>; + cooling-device = <&cpu3_pause 1 1>; + }; }; }; @@ -155,6 +321,19 @@ hysteresis = <5000>; type = "passive"; }; + + gpu0_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu0_cdev { + trip = <&gpu0_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; }; }; @@ -180,6 +359,19 @@ hysteresis = <5000>; type = "passive"; }; + + gpu1_tj_cfg: tj_cfg { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + gpu1_cdev { + trip = <&gpu1_tj_cfg>; + cooling-device = <&msm_gpu 0 THERMAL_NO_LIMIT>; + }; }; }; @@ -205,6 +397,20 @@ hysteresis = <5000>; type = "passive"; }; + + nspss_0_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp0_cdev { + trip = <&nspss_0_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; }; }; @@ -230,6 +436,20 @@ hysteresis = <5000>; type = "passive"; }; + + nspss_1_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp1_cdev { + trip = <&nspss_1_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; }; }; @@ -255,6 +475,20 @@ hysteresis = <5000>; type = "passive"; }; + + nspss_2_config: junction-config { + temperature = <95000>; + hysteresis = <5000>; + type = "passive"; + }; + }; + + cooling-maps { + nsp2_cdev { + trip = <&nspss_2_config>; + cooling-device = <&cdsp_sw THERMAL_NO_LIMIT + THERMAL_NO_LIMIT>; + }; }; }; @@ -288,12 +522,6 @@ type = "passive"; }; - ddr_config0: ddr0-config { - temperature = <90000>; - hysteresis = <5000>; - type = "passive"; - }; - reset-mon-cfg { temperature = <115000>; hysteresis = <5000>; diff --git a/qcom/neo.dtsi b/qcom/neo.dtsi index 8814e9f6..275ad957 100644 --- a/qcom/neo.dtsi +++ b/qcom/neo.dtsi @@ -51,6 +51,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0 4>; + #cooling-cells = <2>; L2_0: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -75,6 +76,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0 4>; + #cooling-cells = <2>; L2_1: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -99,6 +101,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0 4>; + #cooling-cells = <2>; L2_2: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>; @@ -123,6 +126,7 @@ capacity-dmips-mhz = <1024>; dynamic-power-coefficient = <100>; qcom,freq-domain = <&cpufreq_hw 0 4>; + #cooling-cells = <2>; L2_3: l2-cache { compatible = "arm,arch-cache"; cache-level = <2>;