diff --git a/bindings/clock/qcom,dispcc.txt b/bindings/clock/qcom,dispcc.txt
index d8bf1815..feaccf64 100644
--- a/bindings/clock/qcom,dispcc.txt
+++ b/bindings/clock/qcom,dispcc.txt
@@ -8,6 +8,7 @@ Required properties :
 			"qcom,sdm845-dispcc"
 			"qcom,lahaina-dispcc"
 			"qcom,shima-dispcc"
+			"qcom,holi-dispcc"
 
 - reg : shall contain base register location and length.
 - #clock-cells : from common clock binding, shall contain 1.
diff --git a/bindings/clock/qcom,gcc.txt b/bindings/clock/qcom,gcc.txt
index d66630ef..d990a9c1 100644
--- a/bindings/clock/qcom,gcc.txt
+++ b/bindings/clock/qcom,gcc.txt
@@ -29,7 +29,7 @@ Required properties :
 			"qcom,gcc-sa8155"
 			"qcom,gcc-sa8155-v2"
 			"qcom,shima-gcc"
-
+			"qcom,holi-gcc"
 
 - reg : shall contain base register location and length
 - vdd_cx-supply: The vdd_cx logic rail supply.
diff --git a/bindings/clock/qcom,gpucc.txt b/bindings/clock/qcom,gpucc.txt
index a609c98b..4b987a33 100644
--- a/bindings/clock/qcom,gpucc.txt
+++ b/bindings/clock/qcom,gpucc.txt
@@ -4,7 +4,8 @@ Qualcomm Technologies, Inc. Graphics Clock & Reset Controller Binding
 Required properties :
 - compatible : shall contain "qcom,sdm845-gpucc" or "qcom,msm8998-gpucc",
 		"qcom,lahaina-gpucc",
-		"qcom,shima-gpucc".
+		"qcom,shima-gpucc",
+		"qcom,holi-gpucc".
 - reg: shall contain base register offset and size.
 - reg-names: names of registers listed in the same order as in the reg property.
 		Must contain "cc_base".