From 5c8541b27ab2c184e3f3cca9527fb4d122979de5 Mon Sep 17 00:00:00 2001
From: Jaskaran Singh <jasksing@qti.qualcomm.com>
Date: Mon, 7 Feb 2022 11:22:07 +0530
Subject: [PATCH] ARM: dts: msm: Add initial SMMU configuration for Anorak

Add initial apps and gpu SMMU configuration for Anorak.

Change-Id: Ia739dd1a3c4a2870231197faaaf5b910a8c65fe7
---
 qcom/anorak.dtsi              |   2 +
 qcom/msm-arm-smmu-anorak.dtsi | 398 ++++++++++++++++++++++++++++++++++
 2 files changed, 400 insertions(+)
 create mode 100644 qcom/msm-arm-smmu-anorak.dtsi

diff --git a/qcom/anorak.dtsi b/qcom/anorak.dtsi
index 33fb8fb3..79f31130 100644
--- a/qcom/anorak.dtsi
+++ b/qcom/anorak.dtsi
@@ -1065,3 +1065,5 @@
 #include "anorak-dma-heaps.dtsi"
 #include "ipcc-test.dtsi"
 #include "anorak-pcie.dtsi"
+#include "msm-arm-smmu-anorak.dtsi"
+
diff --git a/qcom/msm-arm-smmu-anorak.dtsi b/qcom/msm-arm-smmu-anorak.dtsi
new file mode 100644
index 00000000..d99b700f
--- /dev/null
+++ b/qcom/msm-arm-smmu-anorak.dtsi
@@ -0,0 +1,398 @@
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+
+&soc {
+	kgsl_smmu: kgsl-smmu@3da0000 {
+		compatible = "qcom,qsmmu-v500", "qcom,adreno-smmu";
+		reg = <0x3da0000 0x40000>,
+			<0x3de2000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,num-context-banks-override = <0x6>;
+		qcom,num-smr-override = <0x6>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+
+		qcom,regulator-names = "vdd";
+		vdd-supply = <&gpu_cc_cx_gdsc>;
+
+		clocks = <&gpucc GPU_CC_CX_GMU_CLK>,
+		       <&gpucc GPU_CC_HUB_CX_INT_CLK>,
+		       <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>,
+		       <&gcc GCC_GPU_MEMNOC_GFX_CLK>,
+		       <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>,
+		       <&gpucc GPU_CC_AHB_CLK>;
+		clock-names =
+			"gpu_cc_cx_gmu",
+			"gpu_cc_hub_cx_int",
+			"gpu_cc_hlos1_vote_gpu_smmu",
+			"gcc_gpu_memnoc_gfx",
+			"gcc_gpu_snoc_dvm_gfx",
+			"gpu_cc_ahb";
+
+		qcom,actlr =
+			/* All CBs of GFX: +15 deep PF */
+			<0x000 0x3ff 0x32B>;
+
+		interrupts =	<GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 677 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 688 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 422 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 476 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 574 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 575 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 576 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 577 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 660 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 662 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 665 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 666 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 667 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 670 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 700 IRQ_TYPE_LEVEL_HIGH>;
+
+		gpu_qtb: gpu_qtb@3de8000 {
+			compatible = "qcom,qsmmuv500-tbu", "qcom,qtb500";
+			reg = <0x3de8000 0x1000>;
+			reg-names = "base";
+			qcom,iova-width = <49>;
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,num-qtb-ports = <2>;
+		};
+
+	};
+
+	apps_smmu: apps-smmu@15000000 {
+		compatible = "qcom,qsmmu-v500";
+		reg = <0x15000000 0x100000>,
+			<0x151c6000 0x20>;
+		reg-names = "base", "tcu-base";
+		#iommu-cells = <2>;
+		qcom,skip-init;
+		qcom,use-3-lvl-tables;
+		qcom,handoff-smrs = <0x1000 0x402>;
+		#global-interrupts = <1>;
+		#size-cells = <1>;
+		#address-cells = <1>;
+		ranges;
+		dma-coherent;
+		interrupts =	<GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>,
+				<GIC_SPI 708 IRQ_TYPE_LEVEL_HIGH>;
+
+
+		qcom,actlr =
+			/* For display, camera +0 deep PF */
+			<0x800 0x7ff 0x001>,
+			<0x1000 0x7ff 0x001>,
+
+			/* For camera IFE +3 PF*/
+			<0x3000 0x3ff 0x103>,
+
+			/* For video +3 deep PF */
+			<0x980 0x27 0x103>,
+
+			/* For compute +15 deep PF */
+			<0x961 0x27 0x303>;
+
+		anoc_1_tbu: anoc_1_tbu@151c9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151c9000 0x1000>,
+				<0x151c6200 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x0 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <36>;
+		};
+
+		anoc_2_tbu: anoc_2_tbu@151cd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151cd000 0x1000>,
+				<0x151c6208  0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x400 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <36>;
+		};
+
+		mmnoc_sf_0: mmnoc_sf_0_tbu@151d1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151d1000 0x1000>,
+				<0x151c6210 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x800 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		mmnoc_sf_1: mmnoc_sf_1_tbu@151d5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151d5000 0x1000>,
+				<0x151c6218 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0xc00 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		mdp_00_tbu: mdp_00_tbu@151d9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151d9000 0x1000>,
+				<0x151c6220 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1000 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		mdp_01_tbu: mdp_01_tbu@151dd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151dd000 0x1000>,
+				<0x151c6228 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1400 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		mdp_10_tbu: mdp_10_tbu@151e1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e1000 0x1000>,
+				<0x151c6230 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1800 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		mdp_11_tbu: mdp_11_tbu@151e5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e5000 0x1000>,
+				<0x151c6238 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x1c00 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		nsp_0_tbu: nsp_0_tbu@151e9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151e9000 0x1000>,
+				<0x151c6240 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2000 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		nsp_1_tbu: nsp_1_tbu@151ed000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151ed000 0x1000>,
+				<0x151c6248 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2400 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		lpass_tbu: lpass_tbu@151f1000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f1000 0x1000>,
+				<0x151c6250 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2800 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		anoc_pcie_tbu: anoc_pcie_tbu@151f5000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f5000 0x1000>,
+				<0x151c6258 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x2c00 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <36>;
+		};
+
+		camnoc_hf_0_tbu: camnoc_hf_0_tbu@151f9000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151f9000 0x1000>,
+				<0x151c6260 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x3000 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+
+		camnoc_hf_1_tbu: camnoc_hf_1_tbu@151fd000 {
+			compatible = "qcom,qsmmuv500-tbu";
+			reg = <0x151fd000 0x1000>,
+				<0x151c6268 0x8>;
+			reg-names = "base", "status-reg";
+			qcom,stream-id-range = <0x3400 0x400>;
+			qcom,micro-idle;
+			qcom,iova-width = <32>;
+		};
+	};
+
+	dma_dev@0x0 {
+		compatible = "qcom,iommu-dma";
+		memory-region = <&system_cma>;
+	};
+
+	iommu_test_device {
+		compatible = "qcom,iommu-debug-test";
+
+		usecase0_apps {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0>;
+		};
+
+		usecase1_apps_fastmap {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0>;
+			qcom,iommu-dma = "fastmap";
+		};
+
+		usecase2_apps_atomic {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0>;
+			qcom,iommu-dma = "atomic";
+		};
+
+		usecase3_apps_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e1 0>;
+			dma-coherent;
+		};
+
+		usecase4_apps_secure {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&apps_smmu 0x3e0 0x0>;
+			qcom,iommu-dma = "atomic";
+			qcom,iommu-vmid = <0xA>; /* VMID_CP_PIXEL */
+		};
+
+		usecase5_kgsl {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x0007 0x0>;
+		};
+
+		usecase6_kgsl_dma {
+			compatible = "qcom,iommu-debug-usecase";
+			iommus = <&kgsl_smmu 0x0007 0x0>;
+			dma-coherent;
+		};
+
+	};
+};