From 6206eb2f06788c6d7049358554d756b8a0ede7b1 Mon Sep 17 00:00:00 2001 From: Harshitha Sai Neelati Date: Thu, 28 Oct 2021 10:42:34 +0530 Subject: [PATCH] ARM: dts: msm: Add apb_pclk to diwali clock list Add apb_pclk to diwali clock list for qdss support. Change-Id: Ibf57ce68bbafa1753956bbd423eb3235d9a09249 --- qcom/diwali-gpu.dtsi | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/qcom/diwali-gpu.dtsi b/qcom/diwali-gpu.dtsi index e7287547..a1036caa 100644 --- a/qcom/diwali-gpu.dtsi +++ b/qcom/diwali-gpu.dtsi @@ -22,7 +22,8 @@ <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, <&gpucc GPU_CC_CX_GMU_CLK>, <&gpucc GPU_CC_HUB_AON_CLK>, - <&gpucc GPU_CC_HUB_CX_INT_CLK>; + <&gpucc GPU_CC_HUB_CX_INT_CLK>, + <&aoss_qmp>; clock-names = "gcc_gpu_memnoc_gfx", "gcc_gpu_snoc_dvm_gfx", @@ -30,7 +31,8 @@ "gpu_cc_hlos1_vote_gpu_smmu", "gpu_cc_cx_gmu", "gpu_cc_hub_aon", - "gpu_cc_hub_cx_int"; + "gpu_cc_hub_cx_int", + "apb_pclk"; qcom,chipid = <0x06060201>; @@ -253,9 +255,11 @@ <&gcc GCC_GPU_MEMNOC_GFX_CLK>, <&gpucc GPU_CC_AHB_CLK>, <&gpucc GPU_CC_HUB_CX_INT_CLK>, - <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; + <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, + <&aoss_qmp>; clock-names = "gmu_clk", "cxo_clk", "axi_clk", - "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote"; + "memnoc_clk", "ahb_clk", "hub_clk", "smmu_vote", + "apb_pclk"; }; };