From 64065c4c1dfc651e23c868d207d4d77b94eab4ed Mon Sep 17 00:00:00 2001 From: Krishna Chaitanya Chundru Date: Fri, 6 Jan 2023 15:16:37 +0530 Subject: [PATCH] ARM: dts: msm: Add EP configuration for PCIe1 neo Add PCIe1 EP related configuration for neo target. Change-Id: If1feae7a8dbfc015bde6a44acf4275572f0b73f3 --- qcom/neo-pcie.dtsi | 224 ++++++++++++++++++++++++++++++++++++++++++ qcom/neo-pinctrl.dtsi | 54 ++++++++++ 2 files changed, 278 insertions(+) diff --git a/qcom/neo-pcie.dtsi b/qcom/neo-pcie.dtsi index 2d559836..5cf736eb 100644 --- a/qcom/neo-pcie.dtsi +++ b/qcom/neo-pcie.dtsi @@ -579,4 +579,228 @@ , ; }; + + pcie1_edma: qcom,pcie1_edma@40002000 { + compatible = "qcom,pci-edma"; + #dma-cells = <2>; + reg = <0x40002000 0x2000>; + interrupt-parent = <&intc>; + interrupts = ; + interrupt-names = "pci-edma-int"; + status = "disabled"; + }; + + pcie_ep: qcom,pcie@40002000 { + compatible = "qcom,pcie-ep"; + + reg = <0x40004000 0x1000>, + <0x40000000 0xf1d>, + <0x40000f20 0xa8>, + <0x40001000 0x1000>, + <0x40002000 0x2000>, + <0x01c08000 0x3000>, + <0x01c0e000 0x2000>, + <0x01c0b000 0x1000>; + reg-names = "msi", "dm_core", "elbi", "iatu", "edma", "parf", + "phy", "mmio"; + + #address-cells = <0>; + interrupt-parent = <&pcie_ep>; + interrupts = <0>; + #interrupt-cells = <1>; + interrupt-map-mask = <0xffffffff>; + interrupt-map = <0 &intc GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "int_global"; + + pinctrl-names = "default", "sleep"; + pinctrl-0 = <&pcie_ep_clkreq_default &pcie_ep_perst_default + &pcie_ep_wake_default>; + pinctrl-1 = <&pcie_ep_clkreq_sleep &pcie_ep_perst_default + &pcie_ep_wake_default>; + + clkreq-gpio = <&tlmm 59 GPIO_ACTIVE_HIGH>; + perst-gpio = <&tlmm 58 GPIO_ACTIVE_HIGH>; + wake-gpio = <&tlmm 60 GPIO_ACTIVE_HIGH>; + + gdsc-vdd-supply = <&gcc_pcie_1_gdsc>; + gdsc-phy-vdd-supply = <&gcc_pcie_1_phy_gdsc>; + vreg-1p8-supply = <&pm8150_l3>; + vreg-0p9-supply = <&pm8150_l8>; + vreg-cx-supply = <&VDD_CX_LEVEL>; + vreg-mx-supply = <&VDD_MXA_LEVEL>; + + qcom,vreg-1p8-voltage-level = <1200000 1200000 15600>; + qcom,vreg-0p9-voltage-level = <880000 880000 54200>; + qcom,vreg-cx-voltage-level = ; + qcom,vreg-mx-voltage-level = ; + + clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, + <&gcc GCC_PCIE_1_CFG_AHB_CLK>, + <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, + <&gcc GCC_PCIE_1_SLV_AXI_CLK>, + <&gcc GCC_PCIE_1_AUX_CLK>, + <&tcsrcc TCSR_PCIE_1_CLKREF_EN>, + <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, + <&gcc GCC_DDRSS_PCIE_SF_CLK>, + <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>, + <&gcc GCC_PCIE_1_PHY_RCHNG_CLK>, + <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, + <&pcie_1_pipe_clk>, + <&rpmhcc RPMH_CXO_CLK>; + + clock-names = "pcie_pipe_clk", "pcie_cfg_ahb_clk", + "pcie_mstr_axi_clk", "pcie_slv_axi_clk", + "pcie_aux_clk", "pcie_ldo", + "pcie_slv_q2a_axi_clk", "pcie_ddrss_sf_tbu_clk", + "pcie_aggre_noc_0_axi_clk", + "pcie_phy_refgen_clk", "pcie_pipe_clk_mux", + "pcie_pipe_clk_ext_src", + "pcie_0_ref_clk_src"; + + resets = <&gcc GCC_PCIE_1_BCR>, + <&gcc GCC_PCIE_1_PHY_BCR>; + + reset-names = "pcie_core_reset", + "pcie_phy_reset"; + + interconnect-names = "icc_path"; + interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + + qcom,pcie-vendor-id = /bits/ 16 <0x17cb>; + qcom,pcie-device-id = /bits/ 16 <0x0111>; + qcom,tcsr-not-supported; + qcom,pcie-aggregated-irq; + qcom,pcie-mhi-a7-irq; + qcom,pcie-link-speed = <3>; + qcom,pcie-phy-ver = <8>; + qcom,pcie-active-config; + qcom,phy-status-reg2 = <0x218>; + qcom,pcie-perst-enum; + + qcom,phy-init = <0x0240 0x01 0x0 + 0x0110 0x00 0x0 + 0x00bc 0x06 0x0 + 0x00e4 0x07 0x0 + 0x00f4 0x07 0x0 + 0x0070 0x28 0x0 + 0x0010 0x28 0x0 + 0x0074 0x0d 0x0 + 0x0014 0x0d 0x0 + 0x0078 0x00 0x0 + 0x0018 0x00 0x0 + 0x0120 0x42 0x0 + 0x0080 0xff 0x0 + 0x0084 0x04 0x0 + 0x0020 0xff 0x0 + 0x0024 0x09 0x0 + 0x0088 0x19 0x0 + 0x0028 0x14 0x0 + 0x00a0 0xfb 0x0 + 0x00a4 0x03 0x0 + 0x0040 0xfb 0x0 + 0x0044 0x03 0x0 + 0x0140 0x14 0x0 + 0x003c 0x01 0x0 + 0x001c 0x04 0x0 + 0x0174 0x16 0x0 + 0x0188 0x14 0x0 + 0x0170 0xa0 0x0 + 0x11a4 0x38 0x0 + 0x10dc 0x11 0x0 + 0x1160 0xbf 0x0 + 0x1164 0xbf 0x0 + 0x1168 0xb7 0x0 + 0x116c 0xea 0x0 + 0x115c 0x3f 0x0 + 0x1174 0x5c 0x0 + 0x1178 0x9c 0x0 + 0x117c 0x1a 0x0 + 0x1180 0x89 0x0 + 0x1170 0xdc 0x0 + 0x1188 0x94 0x0 + 0x118c 0x5b 0x0 + 0x1190 0x1a 0x0 + 0x1194 0x89 0x0 + 0x10cc 0x00 0x0 + 0x1008 0x09 0x0 + 0x1014 0x05 0x0 + 0x104c 0x08 0x0 + 0x1050 0x08 0x0 + 0x10d8 0x0f 0x0 + 0x1118 0x1c 0x0 + 0x10f8 0x07 0x0 + 0x11f8 0x08 0x0 + 0x0e84 0x15 0x0 + 0x0e90 0x3f 0x0 + 0x0ee4 0x02 0x0 + 0x0e40 0x06 0x0 + 0x0e3c 0x18 0x0 + 0x19a4 0x38 0x0 + 0x18dc 0x11 0x0 + 0x1960 0xbf 0x0 + 0x1964 0xbf 0x0 + 0x1968 0xb7 0x0 + 0x196c 0xea 0x0 + 0x195c 0x3f 0x0 + 0x1974 0x5c 0x0 + 0x1978 0x9c 0x0 + 0x197c 0x1a 0x0 + 0x1980 0x89 0x0 + 0x1970 0xdc 0x0 + 0x1988 0x94 0x0 + 0x198c 0x5b 0x0 + 0x1990 0x1a 0x0 + 0x1994 0x89 0x0 + 0x18cc 0x00 0x0 + 0x1808 0x09 0x0 + 0x1814 0x05 0x0 + 0x184c 0x08 0x0 + 0x1850 0x08 0x0 + 0x18d8 0x0f 0x0 + 0x1918 0x1c 0x0 + 0x18f8 0x07 0x0 + 0x19f8 0x08 0x0 + 0x1684 0x15 0x0 + 0x1690 0x3f 0x0 + 0x16e4 0x02 0x0 + 0x1640 0x06 0x0 + 0x163c 0x18 0x0 + 0x02dc 0x05 0x0 + 0x0388 0x77 0x0 + 0x0398 0x0b 0x0 + 0x06a4 0x1e 0x0 + 0x03e0 0x0f 0x0 + 0x060c 0x14 0x0 + 0x0614 0x07 0x0 + 0x03d0 0x8c 0x0 + 0x0368 0x17 0x0 + 0x1424 0x01 0x0 + 0x1428 0x01 0x0 + 0x0200 0x00 0x0 + 0x0244 0x03 0x0>; + + edma-parent = <&pcie1_edma>; + iommus = <&apps_smmu 0x1e00 0x0>; + qcom,iommu-dma = "bypass"; + qcom,pcie-edma; + status = "disabled"; + }; + + mhi_device: mhi_dev@01c0b000 { + compatible = "qcom,msm-mhi-dev"; + reg = <0x1c0b000 0x1000>; + reg-names = "mhi_mmio_base"; + qcom,mhi-ep-msi = <0>; + qcom,mhi-version = <0x1000000>; + qcom,use-pcie-edma; + dmas = <&pcie1_edma 0 0>, <&pcie1_edma 1 0>; + dma-names = "tx", "rx"; + interrupts = ; + interrupt-names = "mhi-device-inta"; + qcom,mhi-ifc-id = <0x011117cb>; + qcom,mhi-interrupt; + status = "disabled"; + }; }; diff --git a/qcom/neo-pinctrl.dtsi b/qcom/neo-pinctrl.dtsi index 74efbdd2..8a63bb5e 100644 --- a/qcom/neo-pinctrl.dtsi +++ b/qcom/neo-pinctrl.dtsi @@ -626,6 +626,60 @@ }; }; + pcie_ep { + pcie_ep_perst_default: pcie_ep_perst_default { + mux { + pins = "gpio58"; + function = "gpio"; + }; + + config { + pins = "gpio58"; + drive-strength = <2>; + bias-pull-down; + }; + }; + + pcie_ep_clkreq_default: pcie_ep_clkreq_default { + mux { + pins = "gpio59"; + function = "PCIE1_CLK_REQ_N"; + }; + + config { + pins = "gpio59"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie_ep_wake_default: pcie_ep_wake_default { + mux { + pins = "gpio60"; + function = "gpio"; + }; + + config { + pins = "gpio60"; + drive-strength = <2>; + bias-pull-up; + }; + }; + + pcie_ep_clkreq_sleep: pcie_ep_clkreq_sleep { + mux { + pins = "gpio59"; + function = "gpio"; + }; + + config { + pins = "gpio59"; + drive-strength = <2>; + bias-pull-up; + }; + }; + }; + bq256xx_intr: bq256xx_intr { bq256xx_intr_default: bq256xx_intr_default { mux {