From 6bbc68de1ffb4532c1d6c08d8d5f87addccc5ce5 Mon Sep 17 00:00:00 2001 From: Sriharsha Allenki Date: Wed, 22 Sep 2021 15:01:49 +0530 Subject: [PATCH] ARM: dts: msm: Add MHI nodes for waipio endpoint Add MHI nodes to enumerate a waipio device as a PCIe endpoint. Change-Id: I3fd3de4938aa8c43a5e49b94fba2558226b64152 --- qcom/waipio-mhi.dtsi | 41 +++++++++++++++++++++++++++++++++++++++++ qcom/waipio.dtsi | 1 + 2 files changed, 42 insertions(+) create mode 100644 qcom/waipio-mhi.dtsi diff --git a/qcom/waipio-mhi.dtsi b/qcom/waipio-mhi.dtsi new file mode 100644 index 00000000..1b10e990 --- /dev/null +++ b/qcom/waipio-mhi.dtsi @@ -0,0 +1,41 @@ +&pcie1 { + qcom,no-l1ss-supported; +}; + +&pcie1_rp { + #address-cells = <5>; + #size-cells = <0>; + + mhi_0: qcom,mhi@0 { + reg = <0 0 0 0 0 >; + + pci-ids = "17cb:0111"; + + /* controller specific configuration */ + qcom,iommu-group = <&mhi_0_iommu_group>; + + + /* mhi bus specific settings */ + mhi,max-channels = <2>; + mhi,timeout = <2000>; + mhi,name = "sxr"; + + #address-cells = <1>; + #size-cells = <1>; + + interconnects = <&pcie_noc MASTER_PCIE_1 &mc_virt SLAVE_EBI1>; + interconnect-names = "pcie_to_ddr"; + + qcom,mhi-bus-bw-cfg = <0 0>, /* no vote */ + <250000 0>, /* avg bw / AB: 2 GBps, peak bw / IB: no vote */ + <500000 0>, /* avg bw / AB: 4 GBps, peak bw / IB: no vote */ + <1000000 0>, /* avg bw / AB: 8 GBps, peak bw / IB: no vote */ + <2000000 0>; /* avg bw / AB: 16 GBps, peak bw / IB: no vote */ + + mhi_0_iommu_group: mhi_0_iommu_group { + qcom,iommu-dma-addr-pool = <0x20000000 0x1fffffff>; + qcom,iommu-dma = "atomic"; + qcom,iommu-pagetable = "coherent"; + }; + }; +}; diff --git a/qcom/waipio.dtsi b/qcom/waipio.dtsi index 817807ad..4637ca4b 100644 --- a/qcom/waipio.dtsi +++ b/qcom/waipio.dtsi @@ -3655,6 +3655,7 @@ #include "waipio-debug.dtsi" #include "waipio-eva.dtsi" #include "waipio-pcie.dtsi" +#include "waipio-mhi.dtsi" #include "msm-rdbg.dtsi" #include "waipio-gpu.dtsi" #include "waipio-thermal.dtsi"