From 70711694074c52bd5474ce5da17ff21cddd4294f Mon Sep 17 00:00:00 2001 From: Rishabh Bhatnagar Date: Wed, 30 Jun 2021 10:36:21 -0700 Subject: [PATCH] dt-bindings: pmu: Add support for AMU events and cpucp sharing Add support for configuring AMU counters for supported events. Also add support to share pmu configuration between hlos and cpucp. Change-Id: Ic3204a6b646baa19a62f75ba725c0eb4df8b0963 --- bindings/soc/qcom/qcom,pmu.txt | 23 +++++++++++++++++------ 1 file changed, 17 insertions(+), 6 deletions(-) diff --git a/bindings/soc/qcom/qcom,pmu.txt b/bindings/soc/qcom/qcom,pmu.txt index d242d9d4..df115e0f 100644 --- a/bindings/soc/qcom/qcom,pmu.txt +++ b/bindings/soc/qcom/qcom,pmu.txt @@ -8,8 +8,19 @@ Required properties: - qcom,long-counter Specify if the pmu counters are long (64 bit) counters. - qcom,pmu-events-tbl: A list of the pmu events to be configured on the cpus. The first column in the table contains the event id and - the second column contains the a bit mask (cpumask) of + the second column contains a bit mask (cpumask) of cpus for which the event should be configured on. + The third column contains the AMU id for events that are + present as part of AMU counters. The list of ids can be + found in enum amu_counters (include/soc/qcom/pmu_lib.h). + 0xFF represents an invalid id. + The fourth column represents the index in enum + cpucp_ev_idx (include/linux/scmi_pmu.h), which is a + shared enum between hlos and cpucp. This helps + maintain the sequence of events when pmu hardware ids + or cached counts are shared between hlos and cpucp. + 0xFF represents an invalid index, which means this event + is not supposed to be shared between hlos and cpucp. Example: @@ -17,9 +28,9 @@ Example: compatible = "qcom,pmu"; qcom,long-counter; qcom,pmu-events-tbl = - < 0x0008 0xFF >, - < 0x0011 0xFF >, - < 0x0017 0xFF >, - < 0x002A 0xFF >, - < 0x1000 0xFF >; + < 0x0008 0xFF 0x02 0x02 >, + < 0x0011 0xFF 0x01 0x01 >, + < 0x0017 0xFF 0xFF 0x04 >, + < 0x002A 0xFF 0xFF 0xFF >, + < 0x1000 0xFF 0xFF 0xFF >; };