From 47510c4182046f8ea5d23d84f3ee5fe80e306cdd Mon Sep 17 00:00:00 2001
From: Vipin Deep Kaur <vkaur@qti.qualcomm.com>
Date: Tue, 1 Oct 2019 12:19:33 +0530
Subject: [PATCH] dt-bindings: gpi: Add DT bindings for GPI dmaengine driver

Add dt-bindings for GPI dmaengine driver.

Change-Id: Id6bc089fe54559cc5f323b83eba853b2d1826764
---
 bindings/dma/qcom_gpi.txt | 95 +++++++++++++++++++++++++++++++++++++++
 1 file changed, 95 insertions(+)
 create mode 100644 bindings/dma/qcom_gpi.txt

diff --git a/bindings/dma/qcom_gpi.txt b/bindings/dma/qcom_gpi.txt
new file mode 100644
index 00000000..91f73d11
--- /dev/null
+++ b/bindings/dma/qcom_gpi.txt
@@ -0,0 +1,95 @@
+Qualcomm Technologies Inc GPI DMA controller
+
+MSM GPI DMA controller provides DMA capabilities for
+peripheral buses such as I2C, UART, and SPI.
+
+==============
+Node Structure
+==============
+
+Main node properties:
+
+- #dma-cells
+  Usage: required
+  Value type: <u32>
+  Definition: Number of parameters client will provide.  Must be set to 5.
+	1st parameter: channel index, 0 for TX, 1 for RX
+	2nd parameter: serial engine index
+	3rd parameter: bus protocol, 1 for SPI, 2 for UART, 3 for I2C
+	4th parameter: channel ring length in transfer ring elements
+	5th parameter: event processing priority, set to 0 for lowest latency
+
+- compatible
+  Usage: required
+  Value type: <string>
+  Definition: "qcom,gpi-dma"
+
+- reg
+  Usage: required
+  Value type: Array of <u32>
+  Definition: register address space location and size
+
+- reg-name
+  Usage: required
+  Value type: <string>
+  Definition: register space name, must be "gpi-top"
+
+- interrupts
+  Usage: required
+  Value type: Array of <u32>
+  Definition: Array of tuples which describe interrupt line for each GPII
+	instance.
+
+- qcom,max-num-gpii
+  Usage: required
+  Value type: <u32>
+  Definition: Total number of GPII instances available for this controller.
+
+- qcom,gpii-mask
+  Usage: required
+  Value type: <u32>
+  Definition: Bitmap of supported GPII instances in hlos.
+
+- qcom,ev-factor
+  Usage: required
+  Value type: <u32>
+  Definition: Event ring transfer size compare to channel transfer ring. Event
+	ring length = ev-factor * transfer ring size
+
+- iommus
+  Usage: required
+  Value type: <phandle u32 u32>
+  Definition: phandle for apps smmu controller and SID, and mask
+	for the controller.  For more detail please check binding
+	documentation arm,smmu.txt
+
+Optional property:
+- qcom,gpi-ee-offset
+  Usage: optional
+  Value type: u64
+  Definition: Specifies the gsi ee register offset for the QUP.
+
+- qcom,iommu-dma-addr-pool
+  Usage: optional
+  Value type: tuple of <address size>.
+  Definition: Indicates the range of addresses that the dma layer will use.
+
+========
+Example:
+========
+gpi_dma0: qcom,gpi-dma@0x800000 {
+	#dma-cells = <5>;
+	compatible = "qcom,gpi-dma";
+	reg = <0x800000 0x60000>;
+	reg-names = "gpi-top";
+	interrupts = <0 244 0>, <0 245 0>, <0 246 0>, <0 247 0>,
+                <0 248 0>, <0 249 0>, <0 250 0>, <0 251 0>,
+                <0 252 0>, <0 253 0>, <0 254 0>, <0 255 0>,
+                <0 256 0>;
+	qcom,max-num-gpii = <13>;
+	qcom,gpii-mask = <0xfa>;
+	qcom,ev-factor = <2>;
+	iommus = <&apps_smmu 0x0016 0x0>;
+	qcom,iommu-dma-addr-pool = <0x40000000 0xc0000000>;
+	status = "ok";
+};